ARM R4F, r1p3 manual C15, nVAL FIQ Enable Clear Register, nVAL IRQ Enable Clear Register format

System Control Coprocessor

31

C

3 2 1 0

Reserved

Cycle count overflow	Performance monitor counter	P2
		P1
IRQ request disable	overflow IRQ request disables
		P0

Figure 4-48 nVAL IRQ Enable Clear Register format

Table 4-46shows how the bit values correspond with the nVAL IRQ Enable Clear Register.

Table 4-46 nVAL IRQ Enable Clear Register bit functions

Bits	Field	Function
[31]	C	CCNT overflow IRQ request
[30:3]	Reserved	UNP or SBZP
[2]	P2	PMC2 overflow IRQ request
[1]	P1	PMC1 overflow IRQ request
[0]	P0	PMC0 overflow IRQ request

To access the nVAL IRQ Enable Clear Register, read or write CP15 with:

MRC p15, 0, <Rd>, c15, c1, 4 ; Read nVAL IRQ Enable Clear Register MCR p15, 0, <Rd>, c15, c1, 4 ; Write nVAL IRQ Enable Clear Register

On reads, this register returns the current setting. On writes, overflow interrupt requests that are currently enabled can be disabled.

For more information of how to enable IRQ requests on counter overflows, and how the requests are signaled, see c15, nVAL IRQ Enable Set Register on page 4-62.

c15, nVAL FIQ Enable Clear Register

The nVAL FIQ Enable Clear Register disables overflow FIQ requests from any of the PMC Registers, PMC0-PMC2, and CCNT, that are enabled.

The nVAL FIQ Enable Clear Register is:

•A read/write register.

•Always accessible in Privileged mode. The USEREN Register determines access mode, see c9, User Enable Register on page 6-15.

Figure 4-49shows the bit arrangement for the nVAL FIQ Enable Clear Register.

31

C

3 2 1 0

Reserved

Cycle count overflow	Performance monitor counter	P2
		P1
FIQ request disable	overflow FIQ request disables
		P0
	Figure 4-49 nVAL FIQ Enable Clear Register format

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