Level Two Interface

9.6Accessing RAMs using the AXI slave interface

This section describes how to access the TCM and cache RAMs using the AXI slave interface.

Table 9-26shows the bits of the ARUSERS or AWUSERS inputs to use to access RAM or a group of RAMs. Each bit is a one-hot 4-bit input, with each bit corresponding to a particular RAM or group of RAMs.

Table 9-26 RAM region decode

AxUSERS bit

One-hot RAM select

 

 

[3]

Data cache RAMs

 

 

[2]

Instruction cache RAMs

 

 

[1]

B0TCM and B1TCM

 

 

[0]

ATCM

 

 

For the caches and the BTCMs, more decoding is performed depending on the address of the request, ARADDRS for reads and AWADDRS for writes. For more information see:

TCM RAM access on page 9-25

Cache RAM access on page 9-26.

Note

Because AWUSERS and AWADDRS work in the same way as ARUSERS and ARADDRS, the following sections only describe ARUSERS and ARADDRS.

ARM DDI 0363E

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ARM r1p3, R4F manual Accessing RAMs using the AXI slave interface, TCM RAM access on Cache RAM access on