ARM r1p3, R4, R4F 9.6 Accessing RAMs using the AXI slave interface

Level Two Interface
ARM DDI 0363E Copyright ©2009 ARM Limited. All rights reserved. 9-24
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9.6 Accessing RAMs using the AXI slave interface
This section describes how to access the TCM and cache RAMs using the AXI slave interface.
Table9-26 shows the bits of the ARUSERS or AW U S E R S inputs to use to access RAM or a
group of RAMs. Each bit is a one-hot 4-bit input, with each bit corresponding to a particular
RAM or group of RAMs.
For the caches and the BTCMs, more decoding is performed depending on the address of the
request, ARADDRS for reads and AWADDRS for writes. For more information see:
•TCM RAM access on page 9-25
•Cache RAM access on page 9-26.
Note
Because AW U S E R S and AWADDRS work in the same way as ARUSERS and ARADDRS,
the following sections only describe ARUSERS and ARADDRS.
Table9-26 RAM region decod e
AxUSERS bit One-hot RAM select
[3] Data cache RAMs
[2] Instruction cache RAMs
[1] B0TCM and B1TCM
[0] ATCM