ARM R4F, r1p3 manual 6shows the input timing parameters for the debug input ports

AC Characteristics

Table 15-5 AXI slave input port timing parameters (continued)

Input delay	Input
	delay	Signal name
minimum
	maximum
Clock uncertainty	60%	AWPARITYS
Clock uncertainty	60%	WPARITYS
Clock uncertainty	60%	ARPARITYS

Table 15-6shows the input timing parameters for the debug input ports.

Table 15-6 Debug input ports timing parameters

Input delay	Input delay	Signal name
minimum	maximum
Clock uncertainty	50%	DBGEN
Clock uncertainty	50%	NIDEN
Clock uncertainty	50%	EDBGRQ
Clock uncertainty	50%	PCLKENDBG
Clock uncertainty	50%	PSELDBG
Clock uncertainty	50%	PADDRDBG[11:2]
Clock uncertainty	50%	PADDRDBG31
Clock uncertainty	50%	PWDATADBG[31:0]
Clock uncertainty	50%	PENABLEDBG
Clock uncertainty	50%	PWRITEDBG
Clock uncertainty	10%	DBGROMADDR[31:12]
Clock uncertainty	10%	DBGROMADDRV
Clock uncertainty	10%	DBGSELFADDR[31:12]
Clock uncertainty	10%	DBGSELFADDRV
Clock uncertainty	50%	DBGRESTART

Table 15-7shows the input timing parameters for the ETM input ports.

Table 15-7 ETM input ports timing parameters

Input delay	Input delay	Signal name
minimum	maximum
Clock uncertainty	50%	ETMPWRUP
Clock uncertainty	50%	nETMWFIREADY
Clock uncertainty	50%	ETMEXTOUT[1:0]

ARM DDI 0363E	Copyright © 2009 ARM Limited. All rights reserved.	15-6
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