ARM R4F AXI master interface transfers, Strongly Ordered and Device transactions on, Linefills on

Level Two Interface

9.3AXI master interface transfers

The processor conforms to the AXI specification, but it does not generate all the AXI transaction types that the specification permits. This section describes the types of AXI transaction that the Cortex-R4 AXI master does not generate. If you are designing an AXI slave to work only with the Cortex-R4 processor, and there are no other AXI masters in your system, you can take advantage of these restrictions and the interface attributes described above to simplify the slave.

This section also contains tables that show some of the types of AXI burst that the processor generates. However, because a particular type of transaction is not shown here does not mean that the processor does not generate such a transaction.

Note

An AXI slave device connected to the Cortex-R4 AXI master port must be capable of handling every kind of transaction permitted by the AXI specification, except where there is an explicit statement in this chapter that such a transaction is not generated. You must not infer any additional restrictions from the example tables given. Restrictions described here are applicable to the r1p0, r1p1, and r1p2 revisions of the processor, and might not be true for future revisions.

Load and store instructions to Non-cacheable memory might not result in an AXI transfer because the data might either be retrieved from, or merged into the internal store data buffers. The exceptions to this are loads or stores to Strongly Ordered or Device memory. These always result in AXI transfers. See Strongly Ordered and Device transactions on page 9-8.

Restrictions on AXI transfers on page 9-8describes restrictions on the type of transfers that the Cortex-R4 AXI master interface generates. The AXI master port never deasserts the buffered write response and read data channel ready signals, BREADYM and RREADYM. You must not make any other assumptions about the AXI handshaking signals, except that they conform to the AMBA AXI Protocol Specification.

The following sections give examples of transfers generated by the AXI master interface:

•Strongly Ordered and Device transactions on page 9-8

•Linefills on page 9-13

•Cache line write-back (eviction) on page 9-13

•Non-cacheable reads on page 9-13

•Non-cacheable or write-through writes on page 9-15

•AXI transaction splitting on page 9-16

•Normal write merging on page 9-17.

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