ARM R4F Debug Self Address Offset Register format, Debug Self Address Offset Register functions

Debug

The Debug Self Address Offset Register is:

•in CP14 c0, sub-register c2

•a 32 bit read-only register

•accessible in User and Privileged modes.

Figure 11-4shows the bit arrangement of the Debug Self Address Offset Register.

31 12 11 2 1 0

Debug bus self address offset value

Reserved

Valid bits

Figure 11-4 Debug Self Address Offset Register format

Table 11-9shows how the bit values correspond with the Debug Self Address Offset Register functions.

		Table 11-9 Debug Self Address Offset Register functions
Bits	Field	Function
[31:12]	Debug bus self	Indicates bits [31:12] of the two’s complement offset from the debug ROM physical
	address offset value	address to the physical address where the debug registers are mapped.
[11: 2]	Reserved	UNP on reads, SBZP on writes.
[1:0]	Valid bits	Reads b11 if DBGSELFADDRV is set to 1, otherwise reads b00.
		DBGSELFADDRV must be set to 1 if DBGSELFADDR[31:12] is set to a valid
		value.

To use the Debug Self Address Offset Register, read CP14 c0 with:

MRC p14, 0, <Rd>, c2, c0, 0 ; Read Debug Self Address Offset Register

ARM DDI 0363E	Copyright © 2009 ARM Limited. All rights reserved.	11-13
ID013010	Non-Confidential, Unrestricted Access