ARM r1p3, R4, R4F A.4 Interrupt signals, including VIC interface signals

Processor Signal Descriptions
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A.4 Interrupt signals, including VIC interface signals
TableA-3 shows the Interrupt signals including signals used on the VIC interface.
TableA-3 Interrupt signals
Signal Direction Clocking Description
nFIQ Input CLKINa
Anyb
Fast interruptc.
nIRQ Input CLKINa
Anyb
Normal interruptc.
INTSYNCEN Input Tie-off Tie HIGH if the interrupt inputs are asynchronous to CLKIN.
Tie LOW if the interrupt inputs are synchronous to CLKIN.
IRQADDRV Input CLKINd
Anye
Indicates IRQADDR is valid.
IRQADDRVSYNCEN Input Tie-off Tie HIGH if the IRQADDRV input from the VIC is
asynchronous to CLKIN.
Tie HIGH if the IRQADDRV input from the VIC is
synchronous to CLKIN.
IRQADDR [31:2] Input - Address of the IRQ. This signal must be stable when
IRQADDRV is asserted.
IRQACK Output CLKIN Acknowledges interrupt.
nPMUIRQ Output CLKIN Interrupt request by Performance Monitor Unit (PMU).
a. When INTSYNCEN is tied LOW
b. When INTSYNCEN is tied HIGH
c. This signal is level-sensitive and must be held LOW until a suitable interrupt response is received from the processor.
d. When IRQADDRVSYNCEN is tied LOW
e. When IRQADDRVSYCNEN is tied HIGH