ARM r1p3, R4F manual External debug interface, APB signals, Miscellaneous debug signals

Debug

11.10 External debug interface

The system can access memory-mapped debug registers through the processor APB slave port. This section describes the APB interface and the miscellaneous debug input and output signals:

•APB signals

•Miscellaneous debug signals

•Authentication signals on page 11-52.

11.10.1 APB signals

The APB slave port is compliant with the AMBA Advanced Peripheral Bus specification v3 and can be connected to the Debug Access Port (DAP). This APB slave interface supports 32-bits wide data, stalls, slave-generated aborts, and ten address bits [11:2] mapping 4KB of memory. An extra PADDRDBG31 signal indicates to the processor the source of access.

Table A-12 on page A-17shows the external debug interface signals.

11.10.2 Miscellaneous debug signals

This section describes the miscellaneous debug signals.

EDBGRQ

This signal generates a halting debug event, that is, it requests the processor to enter debug state. When this occurs, the DSCR[5:2] method-of-debug entry bits are set to b0100. When EDBGRQ is asserted, it must be held until DBGACK is asserted. Failure to do so leads to Unpredictable behavior of the processor.

DBGACK

The processor asserts DBGACK to indicate that the system has entered debug state. It serves as a handshake for the EDBGRQ signal. The DBGACK signal is also driven HIGH when the debugger sets the DSCR[10] DbgAck bit to 1.

DBGNOPWRDWN

The processor asserts DBGNOPWRDWN when bit [0] of the Device Power down and Reset Control Register is 1. The processor power controller must work in Emulate mode when this signal is HIGH.

DBGROMADDR

The DBGROMADDR signal specifies bits [31:12] of the debug ROM physical address. This is a configuration input and must be tied off or only change while the processor is in reset. In a system with multiple debug ROMs, this address must be tied off to point to the top-level ROM address.

DBGROMADDRV is the valid signal for DBGROMADDR. If the address cannot be determined, DBGROMADDR must be tied off to zero and DBGROMADDRV must be tied LOW. The value of these signals can be read from the Debug ROM Address Register (DRAR).

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