ARM r1p3, R4, R4F 14.17 SVC, BKPT, Undefined, and Prefetch Aborted instructions

Cycle Timings and Interlock Behavior
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14.17 SVC, BKPT, Undefined, and Prefetch Aborted instructions
This section describes the cycle timing behavior for SVC , Undefined instruction, BKPT and
Prefetch Abort.
In all cases the exception is taken in the Wr stage of the pipeline.
SVC and most Undefined
instructions that fail their condition codes take one cycle. A small number of Undefined
instructions that fail their condition codes take two cycles. Table14-22 shows the
SVC , BKPT ,
Undefined, prefetch aborted instructions cycle timing behavior.
Table14-22 SVC, BKPT, Undefined, prefetch aborted instructions cycle timing behavior
Instruction Cycles
SVC (formerly SWI )9
BKPT 9
Prefetch Abort 9
Undefined Instruction 9