Cycle Timings and Interlock Behavior
ARM DDI 0363E Copyright ©2009 ARM Limited. All rights reserved. 14-17
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14.11 Single load and store instructions
This section describes the cycle timing behavior for
LDR
,
LDRHT
,
LDRSBT
,
LDRSHT
,
LDRT
,
LDRB
,
LDRBT
,
LDRSB
,
LDRH
,
LDRSH
,
STR
,
STRT
,
STRB
,
STRBT
,
STRH
, and
PLD
instructions.
Table14-12 shows the cycle timing behavior for stores and loads, other than loads to the PC.
You can replace
LDR
with any of these single load or store instructions. The following rules
apply:
• They are normally single-cycle issue. Both the base and any offset register are Very Early
Regs.
• They are 3-cycle issue if pre-increment addressing with either a negative register offset or
a shift other than LSL #1, 2 or 3 is used. Both the base and any offset register are Very
Early Regs.
• If unaligned support is enabled then accesses to addresses not aligned to the access size
that cross a 64-bit aligned boundary generate two memory accesses, and require an
additional cycle to issue. This extra cycle is required if the final address is potentially
unaligned, even if the final address turns out to be aligned.
•
PLD
(data preload hint instructions) have cycle timing behavior as for load instructions.
Because they have no destination register, the result latency is not-applicable for such
instructions.
• For store instructions
<Rt>
is always a Late Reg.
Table14-13 shows the cycle timing behavior for loads to the PC.
Table14-12 Cycle timing behavior for stores an d loads, other than loads to the PC
Example instruction Cycles Memory
cycles
Result latency
(LDR)
Result
latency
(base
register)
Comments
LDR <Rt>, <addr_md_1cycle>
a1 1 2 1 Aligned access
LDR <Rt>, <addr_md_3cycle>
a3 1 4 3 Aligned access
LDR <Rt>, <addr_md_1cycle>
a2 2 3 2 Potentially unaligned access
LDR <Rt>, <addr_md_3cycle>
a4 2 5 4 Potentially unaligned access
a. See Table14-14 on page 14-18 for an explanation of
<addr_md_1cycle>
and
<addr_md_3cycle>
.
Table14-13 Cycle timing behavior for loads to th e PC
Example instruction Cycles Memory
cycles
Result
latency Comments
LDR pc, [sp, #<imm>] (!)
1 1 - Correctly return stack predicted, or conditional
predicted correctly
LDR pc, [sp], #<imm>
11 -
LDR pc, [sp, #<imm>] (!)
9 1 - Return stack mispredicted, conditional predicted
correctly
LDR pc, [sp], #<imm>
91 -