ARM R4F Single load and store instructions, 13shows the cycle timing behavior for loads to the PC

Cycle Timings and Interlock Behavior

14.11 Single load and store instructions

This section describes the cycle timing behavior for LDR, LDRHT, LDRSBT, LDRSHT, LDRT, LDRB, LDRBT, LDRSB, LDRH, LDRSH, STR, STRT, STRB, STRBT, STRH, and PLD instructions.

Table 14-12shows the cycle timing behavior for stores and loads, other than loads to the PC. You can replace LDR with any of these single load or store instructions. The following rules apply:

•They are normally single-cycle issue. Both the base and any offset register are Very Early Regs.

•They are 3-cycle issue if pre-increment addressing with either a negative register offset or a shift other than LSL #1, 2 or 3 is used. Both the base and any offset register are Very Early Regs.

•If unaligned support is enabled then accesses to addresses not aligned to the access size that cross a 64-bit aligned boundary generate two memory accesses, and require an additional cycle to issue. This extra cycle is required if the final address is potentially unaligned, even if the final address turns out to be aligned.

•PLD (data preload hint instructions) have cycle timing behavior as for load instructions. Because they have no destination register, the result latency is not-applicable for such instructions.

•For store instructions <Rt> is always a Late Reg.

Table 14-12 Cycle timing behavior for stores and loads, other than loads to the PC

				Result
Example instruction	Cycles	Memory	Result latency	latency	Comments
		cycles	(LDR)	(base
				register)
LDR <Rt>, <addr_md_1cycle>a	1	1	2	1	Aligned access
LDR <Rt>, <addr_md_3cycle>a	3	1	4	3	Aligned access
LDR <Rt>, <addr_md_1cycle>a	2	2	3	2	Potentially unaligned access
LDR <Rt>, <addr_md_3cycle>a	4	2	5	4	Potentially unaligned access

a. See Table 14-14 on page 14-18 for an explanation of <addr_md_1cycle> and <addr_md_3cycle>.

Table 14-13shows the cycle timing behavior for loads to the PC.

Table 14-13 Cycle timing behavior for loads to the PC

Example instruction	Cycles	Memory	Result	Comments
		cycles	latency
LDR pc, [sp, #<imm>] (!)	1	1	-	Correctly return stack predicted, or conditional
				predicted correctly
LDR pc, [sp], #<imm>	1	1	-
LDR pc, [sp, #<imm>] (!)	9	1	-	Return stack mispredicted, conditional predicted
				correctly
LDR pc, [sp], #<imm>	9	1	-

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