Debug

writes to ITR are ignored if InstrCompl_l is set to b0

following a successful write to DTRRX, DTRRXfull and DTRRXfull_l are set to b1

following a successful read from DTRTX, DTRTXfull and DTRTXfull_l are cleared to b0

following a successful write to ITR, InstrCompl and InstrCompl_l are cleared to b0.

Debuggers accessing these registers must first read DSCR. This has the side-effect of copying DTRRXfull and DTRTXfull to DTRRXfull_l and DTRTXfull_l. The debugger must then:

write to the DTRRX if the DTRRXfull flag was b0 (DTRRXfull_l is b0)

read from the DTRTX if the DTRTXfull flag was b1 (DTRTXfull_l is b1)

write to the ITR if the InstrCompl_l flag was b1.

However, debuggers can issue both actions together and later determine from the read DSCR value whether the operations were successful.

In Stall mode, the APB accesses to DTRRX, DTRTX, and ITR stall under the following conditions:

writes to DTRRX are stalled until DTRRXfull is cleared

writes to ITR are stalled until InstrCompl is set

reads from DTRTX are stalled until DTRTXfull is set.

Fast mode is similar to Stall mode except that in Fast mode, the processor fetches an instruction from the ITR when a DTRRX write or DTRTX read succeeds. In Stall mode and Nonblocking mode, the processor fetches an instruction from the ITR when an ITR write succeeds.

11.4.6Data Transfer Register

The DTR consists of two separate physical registers:

the DTRRX (Read Data Transfer Register)

the DTRTX (Write Data Transfer Register).

The register accessed is dependent on the instruction used:

writes, MCR and LDC instructions, access the DTRTX

reads, MRC and STC instructions, access the DTRRX.

Note

Read and write are used with respect to the processor.

For information on the use of these registers with the DTRTXfull flag and DTRRXfull flag, see Debug communications channel on page 11-55.The Data Transfer Register, bits [31:0] contain the data to be transferred.

ARM DDI 0363E

Copyright © 2009 ARM Limited. All rights reserved.

11-18

ID013010

Non-Confidential, Unrestricted Access

 

Page 287
Image 287
ARM r1p3, R4F manual Data Transfer Register