Main
Cortex-R4 and Cortex-R4F
Technical Reference Manual Copyright 2009 ARM Limited. All rights reserved.
Contents Cortex-R4 and Cortex-R4F Technical Reference
Preface
Chapter 1 Introduction
Chapter 2 Programmers Model
Chapter 3 Processor Initialization, Resets, and Clocking
Chapter 4 System Control Coprocessor
Chapter 5 Prefetch Unit
Chapter 6 Events and Performance Monitor
Chapter 7 Memory Protection Unit
Chapter 12 FPU Programmers Model
Chapter 13 Integration Test Registers
Chapter 14 Cycle Timings and Interlock Behavior
Chapter 15 AC Characteristics
Appendix A Processor Signal Descriptions
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List of Tables Cortex-R4 and Cortex-R4F Technical Reference
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List of Figures Cortex-R4 and Cortex-R4F Technical Reference
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About this book
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Feedback
Chapter 1 Introduction
1.1 About the processor
1.2 About the architecture
1.3 Components of the processor
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1.4 External interfaces of the processor
1.5 Power management
1.6 Configurable options
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1.7 Execution pipeline stages
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1.8 Redundant core comparison
1.9 Test features
1.10 Product documentation, design flow, and architecture
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1.11 Product revision information
Table1-3 shows the mappings between these various numbers, for all releases.
Chapter 2 Programmers Model
2.1 About the programmers model
2.2 Instruction set states
2.3 Operating modes
2.4 Data types
2.5 Memory formats
2.6 Registers
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Figure 2-3 Register organization
ADD
CMP
MOV
General registers and program counter
Program status registers
2.7 Program status registers
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2.8 Exceptions
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Figure 2-5 Interrupt entry sequence
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2.9 Acceleration of execution environments
2.10 Unaligned and mixed-endian data access support
2.11 Big-endian instruction support
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3.1 Initialization
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3.2 Resets
3.3 Reset modes
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3.4 Clocking
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4.1 About the system control coprocessor
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4.2 System control coprocessor registers
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To access the Processor Feature Register 1 read CP15 with:
Table4-9 shows how the bit values correspond with the Debug Feature Register 0 functions.
Figure 4-14 shows the bit arrangement for Debug Feature Register 0.
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Table4-11 shows how the bit values correspond with the Memory Model Feature Register 1
To access the Memory Model Feature Register 1 read CP15 with:
Figure 4-17 shows the bit arrangement for Memory Model Feature Register 2.
Table4-12 shows how the bit values correspond with the Memory Model Feature Register 2
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To access the Instruction Set Attributes Register 0, read CP15 with:
The Instruction Set Attributes Register 1 is:
Figure 4-20 shows the bit arrangement for Instruction Set Attributes Register 1.
Table4-15 shows how the bit values correspond with the Instruction Set Attribut es Register 1
To access the Instruction Set Attributes Register 1 read CP15 with:
The Instruction Set Attributes Register 2 is:
Figure 4-21 shows the bit arrangement for Instruction Set Attributes Register 2.
Table4-16 shows how the bit values correspond with the Instruction Set Attribut es Register 2
To access the Instruction Set Attributes Register 2 read CP15 with:
The Instruction Set Attributes Register 3 is: a read-only registers
Figure 4-22 shows the bit arrangement for Instruction Set Attributes Register 3.
Table4-17 shows how the bit values correspond with the Instruction Set Attribut es Register 3
To access the Instruction Set Attributes Register 3 read CP15 with:
The Instruction Set Attributes Register 4 is:
Figure 4-23 shows the bit arrangement for Instruction Set Attributes Register 4.
Table4-18 shows how the bit values correspond with the Instruction Set Attribut es Register 4
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Table4-19 shows how the bit values correspond with the Current Cache Size Identification Register.
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Table4-23 shows the purposes of the individual bits in the System Control Register.
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Table4-25 shows how the bit values correspond with the Secondary Auxiliary Control Register
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Table4-32 shows how the bit values correspond with the MPU Region Size and Enable Registers.
To access an MPU Region Size and Enable Register, read or write CP15 with:
The MPU Region Access Control Registers are: read/write registers
Figure 4-36 shows the arrangement of bits in the register.
Table4-33 shows how the bit values correspond with the Region Access Control Register
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Table4-39 shows how the bit values correspond with the BTCM Region Register.
To access the BTCM Region Register, read or write CP15 with:
Figure 4-42 on page 4-59 shows the arrangement of bits in the register.
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Figure 4-54 shows the bit arrangement of the CFLR when it indicates a correctable TCM error.
To access the Correctable Fault Location Register, read or write CP15 with:
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Table4-55 shows how the bit values correspond wi th the Build Options 2 Register.
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To access the Build Options 2 Register, write CP15 with:
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5.1 About the prefetch unit
5.2 Branch prediction
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5.3 Return stack
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6.1 About the events
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6.2 About the PMU
6.3 Performance monitoring registers
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6.4 Event bus interface
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7.1 About the MPU
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7.2 Memory types
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7.3 Region attributes
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7.4 MPU interaction with memory system
7.5 MPU faults
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8.1 About the L1 memory system
Figure 8-1 L1 memory system block diagram
8.2 About the error detection and correction schemes
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8.3 Fault handling
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8.4 About the TCMs
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8.5 About the caches
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Figure 8-3 Nonsequential read operation performed with one RAM access.
Figure 8-4 shows the appropriate bank RAM being selected for a sequential read operation.
Figure 8-4 Sequential read operation performed with one RAM access
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Table8-13 shows the organization of the data cache RAM bits when parity is implemented.
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8.6 Internal exclusive monitor
8.7 Memory types and L1 memory system behavior
8.8 Error detection events
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9.1 About the L2 interface
9.2 AXI master interface
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9.3 AXI master interface transfers
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Table9-15 shows possible values of ARADDRM, ARBURSTM, ARSIZEM, and ARLENM for a Non-cacheable
that transfers one register, an
5).
that transfers five registers (an
or an
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9.4 AXI slave interface
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9.5 Enabling or disabling AXI slave accesses
9.6 Accessing RAMs using the AXI slave interface
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10.1 About power control
10.2 Power management
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Chapter 11 Debug
11.1 Debug systems
11.2 About the debug unit
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11.3 Debug register interface
The CP14 debug instructions are defined as having Opcode_1 set to 0.
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OS Lock The processor does not support OS Lock.
11.4 Debug register descriptions
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Table11-10 shows how the bit values correspond with Debug Status and Control Register
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Table11-15 shows how the bit values correspond with the Debug Run Control Register
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Table11-17 shows how the bit values correspond with the Breakpoint Control Registers
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Table11-20 shows how the bit values correspond with the Watchpoint Control Registers
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Table11-21 shows how the bit values correspond with the OS Lock Status Register functions.
Table11-22 shows how the bit values correspond with the Authentication Status Register
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Table11-24 shows how the bit values correspond with the PRSR functions.
11.5 Management registers
Table11-27 shows how the bit values correspond with the Claim Tag Set Register functions.
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Table11-32 shows fields that are in the Peripheral Identification Registers.
Table11-33 shows how the bit values correspond with the Peripheral ID Register 0 functions.
Table11-34 shows how the bit values correspond with the Peripheral ID Register 1 functions.
Table11-35 shows how the bit values correspond with the Peripheral ID Register 2 functions.
Table11-37 shows how the bit values correspond with the Peripheral ID Register 4 functions.
Table11-36 shows how the bit values correspond with the Peripheral ID Register 3 functions.
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11.6 Debug events
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11.7 Debug exception
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11.8 Debug state
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11.9 Cache debug
11.10 External debug interface
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11.11 Using the debug functionality
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Example 11-7 shows the sequence of instructions for setting a simple breakpoint.
Example 11-8 shows the code for setting a simple aligned watchpoint.
Table11-45 shows some examples.
Example 11-9 shows the code for setting a simple unaligned watchpoint.
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Example 11-12 Leaving debug state
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Example 11-17 Writing the CPSR
Reading memory Example 11-18 shows the code for reading a byte of memory.
Example 11-18 Reading a byte of memory
Example11-19 shows the code for checking for aborts after a memory access.
Example 11-19 Checking for an abort after memory access
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Example 11-22 Changing the DTR access mode
Example 11-23 shows the sequence to read registers in stall mode.
Example 11-23 Reading registers in stall mode
Example 11-24 shows the sequence to write registers in stall mode.
Example 11-24 Writing registers in stall mode
Example11-25 Reading a block of words of memory
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11.12 Debugging systems with energy management capabilities
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12.1 About the FPU programmers model
12.2 General-purpose registers
12.3 System registers
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Table12-4 shows how the bit values correspond with the FPSCR Register functions.
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Table12-5 shows how the bit values correspond with the FPEXC Register functions.
Table12-6 shows how the bit values correspond with the MVFR0 Register functi ons.
Figure 12-6 on page 12-9 shows the bit arrangement of the MVFR1 Register.
Table12-7 shows how the bit values correspond with the MVFR1 Register.
12.4 Modes of operation
12.5 Compliance with the IEEE 754 standard
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13.1 About Integration Test Registers
13.2 Programming and reading Integration Test Registers
13.3 Summary of the processor registers used for integration testing
13.4 Processor integration testing
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13.4.3 ITETMIF Register (ETM interface) The ITETMIF Register at offset
is write-only. Figure13-1 shows the register bit assignments.
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Table13-6 lists the register bit assignments for the ITMISCIN Register.
13.4.6 Integration Mode Control Register (ITCTRL) The ITCTRL Register, register
at offset
, is read/write. Figure 13-4 shows the register bit assignments.
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Chapter 14 Cycle Timings and Interlock Behavior
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14.1 About cycle timings and interlock behavior
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14.2 Register interlock examples
and
Table14-2 shows register interlock examples using
instructions.
instructions take one cycle and have a result latency of one.
14.3 Data processing instructions
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14.4 QADD, QDADD, QSUB, and QDSUB instructions
14.5 Media data-processing
14.6 Sum of Absolute Differences (SAD)
Table14-7 shows
instructions.
and
instructions and gives their cycle timing behavior.
14.7 Multiplies
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14.8 Divide
())(
14.9 Branches
, and
,
This section describes the cycle timing behavior for the
14.10 Processor state updating instructions
14.11 Single load and store instructions
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14.12 Load and Store Double instructions
14.13 Load and Store Multiple instructions
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14.14 RFE and SRS instructions
14.15 Synchronization instructions
14.16 Coprocessor instructions
14.17 SVC, BKPT, Undefined, and Prefetch Aborted instructions
14.18 Miscellaneous instructions
14.19 Floating-point register transfer instructions
14.20 Floating-point load/store instructions
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14.21 Floating-point single-precision data processing instructions
This section describes the cycle timing behavior for all single-precision VFP
, and
,
instructions. This includes arithmetic instructions such as
14.22 Floating-point double-precision data processing instructions
This section describes the cycle timing behavior for all double-precision VFP
, and
,
,
14.23 Dual issue
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Case F2_st
, and
,
instructions,
.
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15.1 Processor timing
15.2 Processor timing parameters
Table15-3 shows the timing parameters for the interrupt input ports.
Table15-4 shows the input timing parameters for the AXI master port.
Table15-5 shows the input timing parameters for the AXI slave port.
Table15-6 shows the input timing parameters for the debug input ports.
Table15-7 shows the input timing parameters for the ETM input ports.
Table15-8 shows the timing parameters for the test input ports.
Table15-9 shows the timing parameters for the TCM interface input ports.
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Table15-13 shows the timing parameters for the AXI slave outpu t ports.
Table15-14 shows the timing parameters for the debug interface output ports.
Table15-15 shows the timing parameters for the ETM interface output ports.
Table15-16 shows the timing parameters for the test output ports.
Table15-17 shows the timing parameters for the TCM interface output ports.
Table15-18 shows the timing parameters for the FPU output signals.
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Appendix A Processor Signal Descriptions
A.1 About the processor signal descriptions
A.2 Global signals
A.3 Configuration signals
TableA-2 shows the processor configuration signals.
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A.4 Interrupt signals, including VIC interface signals
TableA-3 shows the Interrupt signals including signals used on the VIC interface.
A.5 L2 interface signals
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A.6 TCM interface signals
TableA-8 shows the ATCM port signals.
TableA-9 shows the B0TCM port signals.
TableA-10 shows the B1TCM port signals.
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A.7 Dual core interface signals
TableA-11 shows the dual redundant core interface signals.
A.8 Debug interface signals
TableA-13 shows the debug miscellaneous signals.
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A.9 ETM interface signals
TableA-14 shows the ETM interface signals.
A.10 Test signals
TableA-15 shows the test signals.
A.11 MBIST signals
TableA-16 shows the MBIST signals.
A.12 Validation signals
TableA-17 shows the validation signals.
A.13 FPU signals
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B.1 ECC scheme selection guidelines
Appendix C Revisions
This appendix describes the technical changes between released issues of this book.
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Glossary
