R i p h e r a l R E Q a n d D O N E s i g n a l i n g

E X T E R N A L D M A

Peripheral REQ and DONE signaling

Determining the width of PDEN

Peripheral DMA single write access

Use the memory controller’s Static Memory Write Delay register and Static Memory Write Enable Delay register to determine the width of the PDEN assertion.

CLK

st_cs_n[n]

we_n

PDEN

	ADDR &	Addr/Data Valid
	DATA	Addr/Data Valid
	DATA

Peripheral DMA burst write access

CLK

st_cs_n[n]

we_n
PDEN
ADDR &	ADDR0/DATA0	ADDR1/DATA1	ADDR2/DATA2
DATA	ADDR0/DATA0	ADDR1/DATA1	ADDR2/DATA2
DATA

P e r i p h e r a l R E Q a n d D O N E s i g n a l i n g

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The processor treats the REQ and DONE signals as asynchronous, level signals.

REQ signal	The external peripheral can initiate a DMA transfer at any time by asserting the
	REQ signal.
	The external peripheral can pause the DMA transfer at any time by deasserting
	the REQ signal.
	The REQ signal can be deasserted during a transfer but if the peripheral is
	configured for burst access, the burst completes. The DMA transfer control
	logic remains paused until the REQ signal is reasserted.

344Hardware Reference NS9215

NS9215 specifications

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Digi NS9215 manual R i p h e r a l R E Q a n d D O N E s i g n a l i n g, REQ signal

Models: NS9215

Peripheral DMA burst write access

P e r i p h e r a l R E Q a n d D O N E s i g n a l i n g

REQ signal

REQ signal.

logic remains paused until the REQ signal is reasserted.

344Hardware Reference NS9215

NS9215 specifications