E T H E R N E T C O M M U N I C A T I O N M O D U L E

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Multicast address filtering.

 

 

 

 

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Bit field

Register

Active

Default

Modules reset

 

 

state

state

 

 

 

 

 

 

RPETFUN

MAC1

1

0

MAC TX logic

 

 

 

 

 

MIIM

MII Management

1

0

MAC MIIM logic

 

Configuration register

 

 

 

 

 

 

 

 

M u l t i c a s t a d d r e s s f i l t e r i n g

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The RX-WR logic contains a programmable 8-entry multicast address filter that provides more restrictive filtering than that available in the MAC using the SAL. Only multicast addresses that match those programmed into the filter will be accepted.

Filter entries

Each entry in the filter consists of a 48-bit destination address, an enable bit, and a

 

48-bit mask. The mask contains a 1 in each bit position of the address that is used in

 

the address filter.; this is used to extend the range of each entry.

Multicast address

filter registers

Register

Description

 

 

 

 

MFILTL [7:0]

Lower 32 bits of multicast address

 

 

 

 

MFILTH [7:0]

Upper 16 bits of multicast address

 

 

 

 

MCMSKL

Lower 32 bits of multicast address mask

 

 

 

 

MCMSKH [7:0]

Upper 16 bits of multicast address

 

 

 

 

MFILTEN

Per-entry enable bits

 

 

 

Multicast address filtering example 1

To accept only multicast packets with destination address 0x01_00_5E_00_00_00 using entry 0, the registers are set as shown:

Register

Value

Function

 

 

 

MFILTEN

0x1

Enable entry 0

 

 

 

MFILTL0

0x5E_00_00_00

Lower 32 bits of multicast address

 

 

 

MFILTH0

0x01_00

Upper 16 bits of multicast address

 

 

 

MCMSKL0

0xFFFF_FFFF

Include all of the lower 32 bits of the multicast address

 

 

in the comparison.

 

 

 

MCMSKH0

0xFFFF

Include all of the upper 16 bits of the multicast address

 

 

in the comparison

 

 

 

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Digi NS9215 manual L t i c a s t a d d r e s s f i l t e r i n g, Filter entries, Multicast address Filter registers

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