Digi NS9215 manual Frame transmitted OK, Broadcast frame transmitted, Multicast frame transmitted

E T H E R N E T C O M M U N I C A T I O N M O D U L E	. .
Ethernet Transmit Status register..
	.

Register bit

assignment	Bits	Access	Mnemonic	Reset	Description
	D31:16	N/A	Reserved	N/A	N/A
	D15	R	TXOK	0x0	Frame transmitted OK
					When set, indicates that the frame has been delivered to
					and emptied from the transmit FIFO without problems.
	D14	R	TXBR	0x0	Broadcast frame transmitted
					When set, indicates the frame’s destination address was
					a broadcast address.
	D13	R	TXMC	0x0	Multicast frame transmitted
					When set, indicates the frame’s destination address was
					a multicast address.
	D12	R	TXAL	0x0	TX abort — late collision
					When set, indicates that the frame was aborted due to a
					collision that occurred beyond the collision window set
					in the Collision Window/Retry register. If this bit is set,
					the TX_WR logic stops processing frames and sets the
					TXERR bit in the Ethernet Interrupt Status register.
	D11	R	TXAED	0x0	TX abort — excessive deferral
					When set, indicates that the frame was deferred in
					excess of 6071 nibble times in 100 Mbps or 24,287
					times in 0 Mbps mode. This causes the frame to be
					aborted if the excessive deferral bit is set to 0 in MAC
					Configuration Register #2. If TXAED is set, the
					TX_WR logic stops processing frames and sets the
					TXERR bit in the Ethernet Interrupt Status register.
	D10	R	TXAEC	0x0	TX abort — excessive collisions
					When set, indicates that the frame was aborted because
					the number of collisions exceeded the value set in the
					Collision Window/Retry register. If this bit is set, the
					TX_WR logic stops processing frames and sets the
					TXERR bit in the Ethernet Interrupt Status register.
	D09	R	TXAUR	0x0	TX abort — underrun
					When set, indicates that the frame was aborted because
					the TX_FIFO had an underrun. If this bit is set, the

TX_WR logic stops processing frames and sets the

TXERR bit in the Ethernet Interrupt Status register.

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