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Digi NS9215 manual SPI slave timing diagram

Models: NS9215

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SPI slave timing diagram

S E R I A L C O N T RO L M O D U L E : S P I	. .

SPI timing characteristics..
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2The numbers shown here are for a 7.5 Mhz SPI slave interface clock rate.

3The numbers shown here are for a 300 Mhz PLL output frequency. This value must be proportionally increased with a PLL output frequency decrease.

4This parameter does not depend on any clock frequency.

CS#
	Mode3	S11	S12 S13	S18	S19
	Mode3
CLK	Mode0
	Mode0
				S14 S15
SDI
				S16 S17
SDO

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Digi NS9215 manual SPI slave timing diagram

Contents

90000847C Release date 10 April NS9215 Hardware ReferencePage Page Page Contents A p t e r 3 W o r k i n g w i t h t h e C P U 102 105 A p t e r 4 S y s t e m C o n t r o l M o d u l e 137 141 A p t e r 5 M e m o r y C o n t r o l l e r 203 Sram Bit wide configuration 228 229 Hardware Reference NS9215 HT1 315 A p t e r 7 E x t e r n a l D M a 339 Hardware Reference NS9215 A p t e r 9 I / O H u b M o d u l e 363 Hardware Reference NS9215 A p t e r 1 1 S e r i a l C o n t r o l D u l e H D L C 415 Hardware Reference NS9215 A p t e r 1 4 R e a l T i m e C l o c k M o d u l e 459 A p t e r 1 6 T i m i n g 479 A p t e r 1 7 P a c k a g i n g 513 Hardware Reference NS9215 Heading Description PinoutM o r y b u s i n t e r f a c e Pin Signal DescriptionN O U T 2 6 H e r n e t i n t e r f a c e M a C Pin SignalSdram RAS Sdram CASN e r a l p u r p o s e I / O G P I O CTS Uart a DCD Uart aDSR Uart a RXD Uart aCTS Uart C DCD / TXC Uart CI2C SCL PicdbgdatainiCTS Uart B DCD Uart BDSR Uart B RXD Uart BRXD Uart D DSR Uart DRI Uart D TXC / DTR Uart DPin Signal Description PIC1CLKO PIC1CLKIPin Signal Description PIC0CLKO PIC0CLKIPin Signal Description Pin Signal Description Pin Signal Description I/O OD S t e m c l o c kSystem clock drawing S t e m m o d e RTC clock and battery backup drawingSysmode2 Sysmode1 Sysmode0 Description SPI YES S t e m r e s e tA G T e s t Adcvss POR VSS R a n d b a t t e r y b a c k e d l o g i cGND W e r a n d g r o u n dPower and ground N t r o l a n d S t a t u s r e g i s t e r s Address Description Access Reset valueSystem memory bus I/O control Register address MapControl and Status registers I O C o n f i g u r a t i o n r e g i s t e r s Gpio configuration optionsBits Mnemonic Description Configuration Register #1 Configuration Register #0Bits Access Mnemonic Reset Description Address A0902000Configuration Register #3 Configuration Register #2Address A0902008 Address A090200CConfiguration Register #5 Configuration Register #4Address A0902010 Address A0902014Configuration Register #7 Configuration Register #6Address A0902018 Address A090201CConfiguration Register #9 Configuration Register #8Address A0902020 Address A0902024Configuration Register #11 Configuration Register #10Address A0902028 Address A090202CConfiguration Register #13 Configuration Register #12Address A0902030 Address A0902034Configuration Register #15 Configuration Register #14Address A0902038 Address A090203CConfiguration Register #17 Configuration Register #16Address A0902040 Address A0902044Configuration Register #19 Configuration Register #18Address A0902048 Address A090204CConfiguration Register #21 Configuration Register #20Address A0902050 Address A0902054Configuration Register #23 Configuration Register #22Address A0902058 Address A090205CConfiguration Register #25 Configuration Register #24Address A0902060 GPIOAddress A0902064Address A0902068 Configuration Register #26Gpio Control I O C o n t r o l r e g i s t e r sAddress A090206C Address A0902070 Address A0902074 Address A0902078 Gpio Status I O S t a t u s r e g i s t e r sAddress A0902080 Address A0902084 Address A0902088 M o r y B u s C o n f i g u r a t i o n r e g i s t e rAddress A090208C CS1 CS0CS2 CS3High data bus pullup control Apudis Memory Bus Configuration register About the processor Working with the CPUS t r u c t i o n s e t s Process block DiagramArm926EJ-S ARM instruction set Thumb instruction setJava instruction set Accessing CP15 registersARM926EJ-S system addresses Address manipulation example Mnemonics for these instructions are Terms and abbreviationsTerm Abbreviation Description For readsRegister summary Be ZERO, does not cause any physical damage to the chipRegister Reads Writes TLBWriting to register R0 is Unpredictable This is the contents of the ID code registerR0 ID code Any value other than 1 or 2. Note this exampleDsize and Isize fields Cache type register and field descriptionField contains these bits Field DescriptionSize field Cache size O n t r o l r e g i s t e rAssoc field Associativity Len field Cache line lengthBit functionality Control registerBits Name Function DCache behavior ICacheCache BehaviorAccess permissions and instructions CRm and opcode2 fields should be Zero when writing to R2R a n s l a t i o n T a b l e B a s e r e g i s t e r O m a i n a c c e s s C o n t r o l r e g i s t e rAccess instructions Fault S t a t u s r e g i s t e r sE g i s t e r Register bitsStatus and domain fields Fault a d d r e s s r e g i s t e rPriority Source Size Status Domain Function Description A c h e O p e r a t i o n s r e g i s t e rFunction/operation Data format Instruction Cache operation functionsMVA Modified virtual address format MVA Set/Way format Set/Way example Test and clean DCache instructionsL B O p e r a t i o n s r e g i s t e r Test, clean, and invalidate DCache instructionUnpredictable Operation Data InstructionModified virtual address format MVA A c h e L o c k d o w n r e g i s t e rCache ways That allows you to control each cache way independentlyInstruction or data lockdown register AccessInstructions Modifying the Cache Lockdown register Register formatFor each of the cache lines to be locked down in cache way 0 T L B L o c k d o w n r e g i s t e r Cache unlock procedureBit Which region the TLB entry is placed3 P r o c e s s I D r e g i s t e r 1 a n d R 1 2 r e g i s t e r sProgramming instructions Sample code sequence Use these instructions to program the TLB Lockdown registerPerforming a fast context switch Fcse PID register Access instructionsRegister format This is the format of the Fcse PID register Function Data ARM instructionAccessing reading or writing this register is reserved Context ID register Access instructions4 r e g i s t e r 5 T e s t a n d d e b u g r e g i s t e rM o r y M a n a g e m e n t U n i t M M U MMU FeaturesState space servo control Protection schemeAccess permissions and domains Translated entries Register Bits Description MMU program accessible registers Address translationTTB register Format Translation table baseFirst-level fetch Table walk processFirst-level descriptor First-level fetch concatenation and addressTable descriptors Bits Section Coarse Fine Description Section descriptor FormatValue Meaning Description Fine page table Section descriptor Bit descriptionDescriptor Bits Description113 Second-level descriptor pages Second-level descriptor Second-level descriptor formatSecond-level descriptor least significant bits Second-level descriptor bit assignmentsBits Large Small Tiny Description Translation sequence for large page references Translating sequence for small page references References Translation Sequence for tinyLevel descriptor More informationU Fault s a n d C P U a b o r t s Domain Fault Address register Priority encoding table Fault Address register FARFAR values for Multi-word TransfersSpecifying access permissions Compatibility issuesInterpreting access permission bits M a i n a c c e s s c o n t r o lPrivileged permissions User permissions Fault c h e c k i n g s e q u e n c eNo access 00 Reserved Check domain status Fault checking sequence A b l i n g a n d d i s a b l i n g t h e M M U T e r n a l a b o r t sEnabling Disabling B s t r u c t u r eC h e s a n d w r i t e b u f f e r Cache featuresWrite buffer Enabling the caches Settings Bit settingsR1 register C and M bits for DCache DCacheDescription ARM926EJ-S behavior Table C Table B Bit C h e M V a a n d S e t / W a y f o r m a t sGeneric, virtually indexed, virtually addressed cache Cache format ARM926EJ-SThis figure N c a c h a b l e i n s t r u c t i o n f e t c h e sFor example, with a 4-way cache a = Self-modifying codeAHB behavior Instruction Memory Barrier Sample IMB sequences Noncachable instruction fetches S i n t e r c o n n e c t i o n FeaturesS t e m b u s a r b i t e r Until the transaction completes OwnershipMaster will not occupy the system bus Locked bus sequence Relinquishing the busSplit transfers Arbiter configuration example Address range Size System functions D r e s s d e c o d i n gO g r a m m a b l e t i m e r s Software watchdog timerMaster Name Hmaster30 assignment N e r a l p u r p o s e t i m e r s / c o u n t e r s Gptc characteristics Control fieldSource clock frequency S i c P W M f u n c t i o n Bit mode optionsA d r a t u r e d e code r f u n c t i o n H a n c e d P W M f u n c t i o nSample enhanced PWM waveform NC No change CW Clockwise CCW Counter clockwise Err Error Input signalsQuadrature Encoding truth CCWTimer support Testing signalsMonitors how far the encoder has moved Typical application Digital filterFIQ interrupts T e r r u p t c o n t r o l l e rIRQ interrupts VectorIRQ FIQ IRQ characteristics Interrupt sourcesInterrupt ID Interrupt source Interrupt sources are assigned as shownL c o n f i g u r a t i o n N f i g u r a b l e s y s t e m a t t r i b u t e sConfiguring the powerup settings PLL configuration and control system block diagramO t s t r a p i n i t i a l i z a t i o n Pin name Configuration bits Offset 3124 2316 158 S t e m c o n f i g u r a t i o n r e g i s t e r s155 Isaddr System Memory Chip Select 0 Dynamic Memory Mask C 0 , B R C 1 , B R C 2 , a n d B R C 3 r e g i s t e r s N e r a l a r b i t e r C o n t r o l r e g i s t e rAddress A090 RegisterChannel enable bit B Error D e t e c t S t a t u sChannel allocation Register Register bit assignment This is how the channels are assigned in the four registersEDS1 Address A090 001CNot reset CPU data error Not reset CPU instruction errorNot reset AHB error response Transaction type write or readAHB Slave Error Response Detect Config AHB Error Interrupt ClearM e r M a s t e r C o n t r o l r e g i s t e r EICTimer 9 low step enable Timer 9 reload step enableTimer 9 high step enable Timer 8 reload step enableAddresses A090 0190 / 0194 / 0198 / 019C / 01A0 M e r 0 4 C o n t r o l r e g i s t e r sCapture and compare mode functions Timer enableDebug mode Timer clock selectAddress A090 01A4 M e r 5 C o n t r o l r e g i s t e rTM2 Reload modeAddresses A090 01A8 / 01AC / 01B0 / 01B4 M e r 6 9 C o n t r o l r e g i s t e r sD3118 Reserved D1716 M e r 6 9 H i g h r e g i s t e r s M e r 6 9 L o w r e g i s t e r s M e r 6 9 R e l o a d S t e p r e g i s t e r s M e r 6 9 H i g h a n d L o w S t e p r e g i s t e r sHigh step direction High stepReload step Reload step directionM e r 0 9 R e a d a n d C a p t u r e r e g i s t e r Interrupt Vector Address register Individual register mappingRegister 3124 2316 1508 0700 A D D R r e g i s t e r Interrupt enableInvert Interrupt typeT e r r u p t S t a t u s a c t i v e Interrupt service routine addressInterrupt status active ISAF t w a r e W a t c h d o g C o n f i g u r a t i o n T e r r u p t S t a t u s R a wAddress A090 016C IsrawSoftware watchdog timer clock select Software watchdog enableF t w a r e W a t c h d o g T i m e r Software watchdog interrupt clearO c k C o n f i g u r a t i o n r e g i s t e r Watchdog timerAddress A090 017C Max clock scale control Clock scale controlCPU clock select Memory clock outIO hub D u l e R e s e t r e g i s t e rEthernet MAC Reset status Module Reset register resets each module on the AHB busRST Stat I2CMiscellaneous System Configuration and Status register Endian mode Boot modeMisaligned bus address response mode Internal register access mode bitPLL frequency formula Register Register bit assignment L C o n f i g u r a t i o n r e g i s t e rPLL bypass Address A090 018C W e r M a n a g e m e n tIntid Interrupt IDNew designs should not use this bit Deprecated Chip sleep enableHardware clock scale control Sdram self refresh controlRTC wakeup CPU wake interrupt clearI2C wakeup SPI wakeupAddress A090 022C B B u s a c t i v i t y S t a t u sAddresses A090 01D0 / 01D4 Registers Chip select 0 disableAddresses A090 01D8 / 01DC Chip select 0 baseAddresses A090 01E0 / 01E4 Chip select 1disableChip select 1 base Addresses A090 01E8 / 01EC Chip select 2 disableChip select 2 base Addresses A090 01F0 / 01F4 Chip select 3 disableChip select 3 base Chip select 0 mask Addresses A09001F8 / 01FCAddresses A090 0200 Chip select 1 disableAddresses A090 0208 / 020C N I D r e g i s t e r STS GenidStatus CLRC M o d u l e C o n t r o l r e g i s t e r RTC standby mode statusRTC Module Control register controls the RTC module PolarityRTC clock ready interrupt status RTC standby modeRTC module interrupt status RTC clock ready interrupt clearRTC Module Control register With and without asynchronous page mode Memory controller provides these featuresStatic memory features, such as Amba 32-bit AHB compliancyW p o w e r o p e r a t i o n M o r y m a p Power-on reset memory mapExample Boot from flash Sdram remapped after boot A t i c m e m o r y c o n t r o l l e r Device Write protect Mode BufferROM SramBe aware Write protection Extended wait transfersA t i c m e m o r y i n i t i a l i z a t i o n Access sequencing and memory width Wait state generationMemory mapped peripherals Output enable programmable delay Programmable enableA t i c m e m o r y r e a d c o n t r o l ROM, SRAM, and FlashExternal memory read transfer with two wait states External memory read transfer with zero wait statesTiming parameter Value WAITRD2 WAITOEN0 WAITPAGEN/A WAITWRN/AWAITENN/A WAITTURNN/A External memory read transfers with zero wait statesBurst of two wait states with fixed length Burst of zero wait states with fixed lengthY n c h r o n o u s p a g e m o d e r e a d External memory page mode read transferWAITRD2 WAITOEN0 WAITPAGE1 WAITWRN/A WAITWENN/A WAITTURNN/A External memory 32-bit burst read from 8-bit memoryTiming parameters Value WAITRD0 WAITOEN0 WAITPAGE0 WAITWRN/A WAITWENN/A WAITTURNN/AA t i c m e m o r y w r i t e c o n t r o l Write enable programming delayWait states added between external read and write transfers External memory write transfer with zero wait statesExternal memory write transfer with two wait states WAITRDN/A WAITOENN/A WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN0 S t u r n a r o u n d T i m i n g a n d p a r a m e t e r s S t u r n a r o u n dRead followed by write with no turnaround WAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN0Read followed by a write with two turnaround cycles Write followed by a read with no turnaroundWAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN2 T e l a n e c o n t r o lD r e s s c o n n e c t i v i t y Memory banks constructed from 16-bit memory Memory banks constructed from 16-or 32-bit memory devices2Mx32 ROM N a m i c m e m o r y c o n t r o l l e r Access sequencing and memory widthR a M I n i t i a l i z a t i o n Left-shift value -bit wide data bus Sdram RBC Device size Configuration Load Mode register left shiftBit Parameter Parameter description 256M 8M x 16M x 32M x 512M 64M x Signal 16M device 64M device 128M 256M 512M Bit wide ConfigurationDevice Signal Left-shift value -bit wide data bus Sdram BRCBA1 BA0Register map G i s t e r sOnly. Bursting is not allowed Address Register DescriptionTRWL, tRDL N t r o l r e g i s t e r Reset valuesAddress A070 Low-power mode Bits Access Mnemonic DescriptionMemory controller enable Address mirrorN f i g u r a t i o n r e g i s t e r A t u s r e g i s t e rSelf-refresh acknowledge Srefack Write buffer statusEND N a m i c M e m o r y C o n t r o l r e g i s t e rDynamic memory clock enable Sync/Flash reset/power down signal dypwrnSdram initialization Self-refresh request SrefreqRefresh Refresh timerRead data strategy Active to precharge command period tRAS Precharge command period tRPRAS Srex Address A070 003CSelf-refresh exit time tSREX APR Last-data-out to active command time tAPRDAL Data-in to active command tDAL or tAPWAddress A070 004C Active to active command period tRCRFC Auto-refresh period and auto-refresh to active commandPeriod XSR Exit self-refresh to active time commandRRD Load mode register to Active Command TimeActive Bank a to Active Bank B MRDA t i c M e m o r y E x t e n d e d W a i t r e g i s t e r External wait timeoutExample Address A070 0100 / 0120 / 0140Bdmc Write protectAddress mapping AM1Address mapping Memory ConfigurationFor the Dynamic 119 DescriptionFor a chip select connected to Select this mapping Address A070 0104 / 0124 / 0144CAS RAS latency active to read/write delayCAS latency Do not modifyPsmc Buffer enableBsmc Extended waitChip select polarity Byte lane stateMode Bmode Burst modeMemory width Wait output enable Waitoen Wait write enable WaitwenAddress A070 0208 / 0228 / 0248 WwenRead first access wait state Waitrd Nonpage mode read wait states or asynchronous page modeA t i c M e m o r y R e a d D e l a y 0 3 r e g i s t e r s WtrdWtpg Asynchronous page mode read after the first wait stateWtwr Address A070 0218 / 0238 / 0258Write wait states Waitwr Bus turnaround cycles Waitturn WttnStaticMemory Turn Round Delay 0-3 registers Ethernet Communication Module Features Common acronymsEthernet communications module H e r n e t M a CFeature Description MAC module block diagram FeaturesPHY interface mappings A t i o n a d d r e s s l o g i c S a LStation address logic Media Independent InterfaceMAC receiver A t i s t i c s m o d u l eEthernet front- end module EFE H e r n e t f r o n t e n d m o d u l eReceive packet processor Transmit packet processor C e i v e p a c k e t p r o c e s s o rReceive buffer descriptor format Transferring a frame to system memoryReceive buffer descriptor format description Receive buffer descriptor field definitions A n s m i t p a c k e t p r o c e s s o rTransmit buffer Descriptor field Transmit buffer descriptor formatDefinitions Transmitting a frame Transmitted FrameSuccessfully UnsuccessfullyT e r r u p t s H e r n e t s l a v e i n t e r f a c eInterrupt condition Description S e t s Bit field Register Active Default Modules reset StateStatus bits Filter entries L t i c a s t a d d r e s s f i l t e r i n gMulticast address Filter registers Multicast address filtering exampleMulticast address O c k s y n c h r o n i z a t i o nFiltering example Writing to other registersRegister address Filter Eintr RxdptrEintren TxptrAddress A060 H e r n e t G e n e r a l C o n t r o l R e g i s t e r #Enable receive DMA Enable RX packet processingEnable TX packet processing Accept short 64 receive framesEnable initialization of RX buffer descriptors Enable transmit DMAEtxdma ErxinitRX Fifo RAM access MAC host interface soft resetAlign RX data Insert transmit source addressH e r n e t G e n e r a l S t a t u s r e g i s t e r Rxinit H e r n e t T r a n s m i t S t a t u s r e g i s t e rRX initialization complete Broadcast frame transmitted Frame transmitted OKMulticast frame transmitted TX abort late collisionAddress A060 001C H e r n e t R e c e i v e S t a t u s r e g i s t e rReceive frame OK Receive frame size in bytesReceive broadcast frame Receive multicast frameC C o n f i g u r a t i o n R e g i s t e r # Bits Access Mnemonic Reset Definition Receive enableInternal loopback Excess deferralVlan pad enable Auto detect pad enablePad/CRC enable CRC enablePAD operation Table for transmit C k t o B a c k I n t e r P a c k e t G a p r e g i s t e rFrames TypeHalf-duplex mode Full-duplex modeAddress A060 040C Back-to-back inter-packet-gapAddress A060 L l i s i o n W i n d o w / R e t r y r e g i s t e rIPGR1 Non back-to-back inter-packet-gap partCwin X i m u m F r a m e r e g i s t e rCollision window RetxMaximum frame length Reset MII management blockRmiim I M a n a g e m e n t C o m m a n d r e g i s t e r Clocks field SettingsClock select Suppress preambleRegister bit I M a n a g e m e n t a d d r e s s r e g i s t e rIf both Scan and Read are set, Scan takes precedence Automatically scan for read dataI M a n a g e m e n t R e a d D a t a r e g i s t e r I M a n a g e m e n t W r i t e D a t a r e g i s t e rAddress A060 042C MII read data I M a n a g e m e n t I n d i c a t o r s r e g i s t e rMiilf MII link failureRead data not valid A t i o n a d d r e s s r e g i s t e r sNvalid Automatically scan for read data in progressRegister bit assignments for all three registers A t i o n a d d r e s s F i l t e r r e g i s t e rStation Address Register #1 Station Address Register #2PRO G i s t e r H a s h T a b l e sPRM PRAAddress Register Transmit and receive counters A t i s t i c s r e g i s t e r sTR1K Receive byte counter A060 069C Receive statistics Counters addressReceive packet counter A060 06A0 Address Register Receive countersReceive multicast packet counter A060 06A8 Receive FCS error counter A060 06A4Receive broadcast packet counter A060 06AC RbuoReceive code error counter A060 06C4 Receive alignment error counter A060 06BCReceive carrier sense error counter A060 06C8 Receive undersize packet counter A060 06CCTransmit statistics counters address map Receive jabber counter A060 06D8Transmit byte counter A060 06E0 Address Register Transmit countersTransmit packet counter A060 06E4 Transmit excessive collision packet counter A060 Transmit undersize frame counter A060 Transmit oversize frame counter A060These are the General Statistics registers Carry RegisterC1MGV C1MAXC1RBY C1RPKMask register M1RBY M1MGVM1RPK M1RFCMask register Register Address A060 073C0x00000000 RXA Buffer Descriptor Pointer Address A060 0A04RXB Buffer Descriptor Pointer Address A060 0A0C Address A060 0A08RXC Buffer Descriptor Pointer RXD Buffer Descriptor PointerAddress A060 0A10 H e r n e t I n t e r r u p t S t a t u s r e g i s t e rRxovflstat RxbufcRxdonec RxdonebRxdoned RxnobufAddress A060 0A14 H e r n e t I n t e r r u p t E n a b l e r e g i s t e rAddress A060 0A18 Address A060 0A20 Address A060 0A1CAddress A060 0A24 Address A060 0A28 Address A060 0A30 Address A060 0A2CAddress A060 0A38 Address A060 0A34Address A060 0A3C F r e e B u f f e r r e g i s t e rRxfreed RxfreecL t i c a s t a d d r e s s F i l t e r r e g i s t e r s Address A060 0A5C Address A060 0A58Address A060 0A60 Address A060 0A64L t i c a s t a d d r e s s M a s k r e g i s t e r s Address A060 0A94 Address A060 0A90Address A060 0A98 Address A060 0A9CAddress A060 0AB8 Address A060 0AB4Address A060 0ABC Address A060 0AC0Offset+0 B u f f e r D e s c r i p t o r R a MOffset+8 Offset+4Offset+C Address A060 2000 512 locationsM p l e h a s h t a b l e code Pointer to buffer to store hash table Pointer to hash table 337 Sample hash table code A t r a n s f e r s External DMAA b u f f e r d e s c r i p t o r DMA buffer descriptor diagramSource address pointer Buffer length DestinationS c r i p t o r l i s t p r o c e s s i n g R i p h e r a l D M a r e a d a c c e s s Use this equation to compute total access timeDetermining the width of Pden Equation variables Variable DefinitionPeripheral DMA burst read access Peripheral DMA single read accessR i p h e r a l D M a w r i t e a c c e s s REQ signal Peripheral DMA burst write accessREQ signal Logic remains paused until the REQ signal is reassertedStatic ram chip select configuration Done signal Special circumstancesA t i c R a M c h i p s e l e c t c o n f i g u r a t i o n Register name Field Value CommentA B u f f e r D e s c r i p t o r P o i n t e r A C o n t r o l r e g i s t e r Channel go Channel enableSource width Destination widthDestination burst Fly-by modeSource address increment State ResetIndex Normal completion interrupt pending Error completion interrupt pendingBuffer not ready interrupt pending Channel abort interrupt pendingA P e r i p h e r a l C h i p S e l e c t r e g i s t e r Chip select SELDMA Peripheral Chip Select register Processes 32 bits at a time AESIs programmable for 128-, 192-, or 256-bit key lengths Supports ECB, CBC, OFB, CTR, and CCM cipher modesKey size Characteristic 128 192 256 Block diagramS D M a b u f f e r d e s c r i p t o r Data blocksSource address pointer AES buffer descriptor diagramSource buffer length Destination buffer lengthInterrupt I bit Last L bit Full F bit AES op codeB p r o c e s s i n g C r y p t i o nC , C F B , O F B , a n d C T R p r o c e s s i n g CCM mode does not require an initialization vectorM m o d e Nonce buffer ContentsBits CCM mode Hub Module AHB slave A c o n t r o l l e rInterface Servicing RX and FIFOsControl14 Source address pointer Buffer length Control15 WControl13 L Control12 FStatus150 Control110Not applicable A n s m i t D M a e x a m p l eProcess Pointer and IndexSystem Memory Visual exampleUart a register Address map ReservedUart B register Address map Register Offset DescriptionUart D register Address map Uart C register Address mapAD register Address map SPI register Address mapReserved I2C register Address mapIO Hardware Assist register RTC register Address mapIO register Address map Normal completion interrupt pending RX Error completion interrupt pending RXBuffer not ready interrupt pending RX Channel abort interrupt pending RXError completion interrupt pending TX RX Fifo service request interrupt pendingTX Fifo service request interrupt pending RX Fifo overflow interrupt pendingD u l e D M a R X C o n t r o l Flex I/O Channel abortDirect Rxthrs RxbdpRX Fifo threshold D u l e D i r e c t M o d e R X S t a t u s F I F O Full flag D u l e D i r e c t M o d e R X D a t a F I F OIndexen D u l e D M a T X C o n t r o lTxbdp TX Fifo threshold D u l e D i r e c t M o d e T X D a t a F I F OTXD D u l e D i r e c t M o d e T X D a t a L a s t F I F OTxdl 384 Receive error conditions Modem control signal supportCharacter gap timeout DMA transfers to and from system memoryR m a l m o d e o p e r a t i o n Example configurationUart module structure Control register Field Value CommentBaud rates U d r a t e g e n e r a t o rThis table shows the baud rates achieved with CLKref set to Divisor Baud rateR c e d c h a r a c t e r t r a n s m i s s i o n R d w a r e b a s e d f l o w c o n t r o lM w a k e u p o n c h a r a c t e r r e c o g n i t i o n Force character transmission procedure Collecting feedbackAddress Register A p p e r C o n t r o l a n d S t a t u s r e g i s t e r sDLAB=0 DLAB=1Rtsen A p p e r C o n f i g u r a t i o n r e g i s t e rRTS DtrenReceive character-based flow control SoftwareRemote loopback RTS controlT e r r u p t E n a b l e r e g i s t e r Enable force completeRS485 transceiver deassertion control RS485 transceiver assertion controlEnable parity error Enable overflow errorEnable frame error Enable line breakT e r r u p t S t a t u s r e g i s t e r Frame error Parity errorUart interrupt Force completeCharacter match3 Ring indicatorCharacter match2 Character match1Transmit idle Enable receive character gap timerReceive idle Write this field toC e i v e B u f f e r G a P C o n t r o l r e g i s t e r Enable transmit bit rate generationMask Enable character matchData Flowstate Flow control enableFlow control state FLOW4FLOW2 M W a k e u p C o n t r o l r e g i s t e r Force transmit enableRead-only busy CharA n s m i t B y t e C o u n t EnableAddress 90011034 / 90019034 / 90021034 TxcountR T T r a n s m i t B u f f e r R T R e c e i v e B u f f e rRbuff R T B a u d R a t e D i v i s o r M S B R T B a u d R a t e D i v i s o r L S BTbuff BrdlR T I n t e r r u p t E n a b l e r e g i s t e r Enables modem status interruptBrdm EdssiEnables transmit holding register empty interrupt Enables receive line status interruptEnables receive data available interrupt Interrupt identificationR T F I F O C o n t r o l r e g i s t e r Enable the TX and RX FifoR T L i n e C o n t r o l r e g i s t e r Clear all bytes in the TX FifoParity enable Divisor latch access bitSet break, if set TX data is set to Stick parity, operates as followsR T M o d e m C o n t r o l r e g i s t e r Local loopback enable bitR T L i n e S t a t u s r e g i s t e r Automatic flow controlR T M o d e m S t a t u s r e g i s t e r Trailing edge of RI indicator Delta DCD indicatorDelta DSR indicator Delta CTS indicatorUart Modem Status register Hdlc module structure C e i v e a n d t r a n s m i t o p e r a t i o n sT s O c k i n gTransmit operation Transmitter underflowLast byte bit Pattern table T a e n c o d i n gEncoding examples Last byte bit pattern Valid dataTransitions Dpll operation Adjustment ranges and output clocks NRZ and Nrzi encoding Biphase-Level encoding CLK Address Received or a buffer close event occurs, such as end Enable invalid CRC Enable Hdlc interruptEnable valid CRC Local loopbackRabort Enable receive abort errorHdlc interrupt Receive abort errorInvalid CRC Valid CRCHdata L C D a t a R e g i s t e rHdata Hmode L C C o n t r o l R e g i s t e rClock source L C C l o c k D i v i d e r L o w Address 9002911C L C C l o c k D i v i d e r H i g hDivl Divh Clock enableProgrammable SPI mode 0, 1, 2, or Four-wire interface RXD, TXD, CLK, CSMaster mode internal diagnostic loopback Interface SPI moduleSPI module structure I c o n t r o l l e rSPI mode SPI CLK Idle Timing modes Clocking mode diagramsI c l o c k i n g m o d e s Capture edge Drive edgeI c l o c k g e n e r a t i o n SPI master mode SPI slave modeS t e m b o o t o v e r S P I o p e r a t i o n Clock generation samplesAvailable Strapping options Bootmode10 Address widthEEPROM/FLASH header Entry NameEntry Name Description Time to completionThis is the primary SPI Configuration register Configuration registers for the SPI module are located atEnable master loopback mode I C o n t r o l a n d S t a t u s r e g i s t e r sSlave enable SPI modeO c k G e n e r a t i o n r e g i s t e r Discard bytesEnable clock generation Bits Access Mnemonic Reset DivisorRegister programming steps Use this register to define the data rate of the interfaceD3102 Not used Write this field to D01 SPI master timing Parameters I t i m i n g c h a r a c t e r i s t i c sParm Description Min Max Unit SPI master timing diagram SPI slave timing parameters SPI slave timing diagram SPI timing characteristics Y s i c a l I 2 C b u s Interface timing, data structure, and error handlingI2C bus OverviewSlave Description Addres Bit E x t e r n a l a d d r e s s e sC o m m a n d i n t e r f a c e Command Name DescriptionM m a n d T r a n s m i t D a t a r e g i s t e r R e g i s t e r sAddress 9005 RegisterDescription2C Dlen port iicdlen A t u s R e c e i v e D a t a r e g i s t e rProvide new transmit data Scmdl S t e r a d d r e s s r e g i s t e rMcmdl IrqcdA v e a d d r e s s r e g i s t e r Timing parameter for fast-mode Register Address 9005 000CMask the interrupt to the ARM CPU irqdis Master/slave interrupt codes T e r r u p t codesCode Name Master/slave Description I2C master software driver I2C slave high level driver F t w a r e d r i v e rMaster module normal mode, 16- bit O w c h a r t sSlave module normal mode, 16- bit Real Time Clock Module Address 9006 C G e n e r a l C o n t r o l r e g i s t e r2 4 H o u r r e g i s t e r 12/24 clock mode operationCalendar operation Time date, hour, minute, second operationHRT M e r e g i s t e rHRU Address 9006 000C L e n d a r r e g i s t e rM e Alarm r e g i s t e r Alarm E n a b l e r e g i s t e r L e n d a r Alarm r e g i s t e rAddress 9006 001C E n t F l a g s r e g i s t e rMonth event Alarm eventDate event Hour eventMonth interrupt Alarm interruptDate interrupt Hour interruptT e r r u p t D i s a b l e r e g i s t e r T e r r u p t E n a b l e S t a t u s r e g i s t e r Address 9006 002C N e r a l S t a t u s r e g i s t e rGeneral Status register Structure ADC moduleADC control block C D M a p r o c e d u r eC c o n t r o l a n d s t a t u s r e g i s t e r s ADC configuration registers are located at offsetC C o n f i g u r a t i o n r e g i s t e r Interrupt status DMA enableADC channel select C O u t p u t R e g i s t e r s 0 C C l o c k C o n f i g u r a t i o n r e g i s t e rWait Dout E c t r i c a l c h a r a c t e r i s t i c s Parameter Symbola Rating UnitAbsolute maximum ratings CPU / Memory clock Power Parameter Symbol a Rating UnitRecommended operating conditions Inputs E l e c t r i c a l c h a r a c t e r i s t i c sSym Parameter Conditiona Value Unit Sym Parameter Value Unit OuputsNC7SP17 Manufacturer Part Number Description74LVC1G17GW SN74LVC1G17DCM o r y T i m i n g Sdram burst read 16-bit Sdram burst read 16 bit, CAS latency = Sdram burst write 16 bit Sdram burst read 32 bit Sdram burst read 32 bit, CAS latency = Sdram burst write 32-bit Sdram load mode Sdram refresh mode Clock enable timing Parm Description Min Max Unit Static RAM read cycles with 0 wait states Static RAM asynchronous page mode read, Wtpg = Static RAM read cycle with configurable wait states Static RAM sequential write cycles Static RAM write cycle Static write cycle with configurable wait states CPU Slow peripheral acknowledge timingSlow peripheral acknowledge write Slow peripheral acknowledge readEthernet MII timing Ethernet timingI2C timing Standard Mode Fast Mode Parm Description Min Max UnitParm Description Min Max Unit Mod Not SPI TimingSPI master parameters SPI slave parametersTbclk *8 SPI master mode2 and 3 2-byte transfer SPI master mode 0 and 1 2-byte transferSPI slave mode 2 and 3 2-byte transfer SPI slave mode 0 and 1 2-byte transferParm Description Min Typ Unit S e t a n d h a r d w a r e s t r a p p i n g t i m i n gA G t i m i n g O c k t i m i n g Diagram below pertains to clock timingSystem PLL reference clock Timing Clock timing C k a g e PackagingO c e s s o r D i m e n s i o n s C K a G I N G Processor Dimensions V i s i o n C V i s i o n B