Digi NS9215 manual S t u r n a r o u n d T i m i n g a n d p a r a m e t e r s

M E M O R Y C O N T RO L L E R

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Bus turnaround. .

B u s t u r n a r o u n d

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The memory controller can be configured for each memory bank to use external bus turnaround cycles between read and write memory accesses. The WAITTURN field can be programmed for 1 to 16 turnaround wait states, to avoid bus contention on the external memory databus. Bus turnaround cycles are generated between external bus transfers as follows:

Read to read (different memory banks) Read to write (same memory bank) Read to write (different memory banks)

B u s t u r n a r o u n d : T i m i n g a n d p a r a m e t e r s

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This section shows bus turnaround timing diagrams and parameters.

Read followed by write with no turnaround

This diagram shows a zero wait read followed by a zero wait write with default turnaround between the transfers of two cycles because of the timing of the AHB transfers. Standard AHB wait states are added to the transfers, five for the read and three for the write.

clk_out
addr	A	0	B
data	D(A)		D(B)
st_oe_n

cs[n]

st_we-n

Timing parameter Value

WAITRD0

WAITOEN0

WAITPAGEN/A

WAITWR0

WAITWEN0

WAITTURN0

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