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Digi NS9215 manual Sdram burst write 32-bit

Models: NS9215

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T I M I N G

Memory Timing

SDRAM burst write (32-bit)

prechg	ac ti ve	w r d-A	data-B	data-C	dat a-D
cl k_out
	M10	M12
data<31:0>
	M4
addr	N ote- 1	N ote- 2

M5

dat a_mask <3:0>*

M6

dy_c s_n<3:0>

M7

ras _n

M8

c as _n

M9

w e_n

Notes:

1This is the bank and RAS address.

2This is the CAS address.

490Hardware Reference NS9215

Image 490

Digi NS9215 manual Sdram burst write 32-bit

Contents

NS9215 Hardware Reference 90000847C Release date 10 AprilPage Page Page Contents A p t e r 3 W o r k i n g w i t h t h e C P U 102 105 A p t e r 4 S y s t e m C o n t r o l M o d u l e 137 141 A p t e r 5 M e m o r y C o n t r o l l e r 203 Sram Bit wide configuration 228 229 Hardware Reference NS9215 HT1 315 A p t e r 7 E x t e r n a l D M a 339 Hardware Reference NS9215 A p t e r 9 I / O H u b M o d u l e 363 Hardware Reference NS9215 A p t e r 1 1 S e r i a l C o n t r o l D u l e H D L C 415 Hardware Reference NS9215 A p t e r 1 4 R e a l T i m e C l o c k M o d u l e 459 A p t e r 1 6 T i m i n g 479 A p t e r 1 7 P a c k a g i n g 513 Hardware Reference NS9215 Pinout Heading DescriptionPin Signal Description M o r y b u s i n t e r f a c eN O U T 2 6 Sdram RAS Pin SignalH e r n e t i n t e r f a c e M a C Sdram CASN e r a l p u r p o s e I / O G P I O DSR Uart a DCD Uart aCTS Uart a RXD Uart aI2C SCL DCD / TXC Uart CCTS Uart C PicdbgdatainiDSR Uart B DCD Uart BCTS Uart B RXD Uart BRI Uart D DSR Uart DRXD Uart D TXC / DTR Uart DPin Signal Description PIC1CLKI PIC1CLKOPin Signal Description PIC0CLKI PIC0CLKOPin Signal Description Pin Signal Description Pin Signal Description S t e m c l o c k I/O ODSystem clock drawing RTC clock and battery backup drawing S t e m m o d eSysmode2 Sysmode1 Sysmode0 Description S t e m r e s e t SPI YESA G T e s t Adcvss R a n d b a t t e r y b a c k e d l o g i c POR VSSW e r a n d g r o u n d GNDPower and ground System memory bus I/O control Address Description Access Reset valueN t r o l a n d S t a t u s r e g i s t e r s Register address MapControl and Status registers I O C o n f i g u r a t i o n r e g i s t e r s Gpio configuration optionsBits Mnemonic Description Bits Access Mnemonic Reset Description Configuration Register #0Configuration Register #1 Address A0902000Address A0902008 Configuration Register #2Configuration Register #3 Address A090200CAddress A0902010 Configuration Register #4Configuration Register #5 Address A0902014Address A0902018 Configuration Register #6Configuration Register #7 Address A090201CAddress A0902020 Configuration Register #8Configuration Register #9 Address A0902024Address A0902028 Configuration Register #10Configuration Register #11 Address A090202CAddress A0902030 Configuration Register #12Configuration Register #13 Address A0902034Address A0902038 Configuration Register #14Configuration Register #15 Address A090203CAddress A0902040 Configuration Register #16Configuration Register #17 Address A0902044Address A0902048 Configuration Register #18Configuration Register #19 Address A090204CAddress A0902050 Configuration Register #20Configuration Register #21 Address A0902054Address A0902058 Configuration Register #22Configuration Register #23 Address A090205CAddress A0902060 Configuration Register #24Configuration Register #25 GPIOAddress A0902064Configuration Register #26 Address A0902068Gpio Control I O C o n t r o l r e g i s t e r sAddress A090206C Address A0902070 Address A0902074 Address A0902078 Gpio Status I O S t a t u s r e g i s t e r sAddress A0902080 Address A0902084 Address A0902088 M o r y B u s C o n f i g u r a t i o n r e g i s t e rAddress A090208C CS2 CS0CS1 CS3High data bus pullup control Apudis Memory Bus Configuration register Working with the CPU About the processorArm926EJ-S Process block DiagramS t r u c t i o n s e t s ARM instruction set Thumb instruction setJava instruction set Accessing CP15 registersARM926EJ-S system addresses Address manipulation example Term Abbreviation Description Terms and abbreviationsMnemonics for these instructions are For readsRegister Reads Writes Be ZERO, does not cause any physical damage to the chipRegister summary TLBR0 ID code This is the contents of the ID code registerWriting to register R0 is Unpredictable Any value other than 1 or 2. Note this exampleField contains these bits Cache type register and field descriptionDsize and Isize fields Field DescriptionAssoc field Associativity O n t r o l r e g i s t e rSize field Cache size Len field Cache line lengthBit functionality Control registerBits Name Function Cache ICacheDCache behavior BehaviorR a n s l a t i o n T a b l e B a s e r e g i s t e r CRm and opcode2 fields should be Zero when writing to R2Access permissions and instructions O m a i n a c c e s s C o n t r o l r e g i s t e rE g i s t e r Fault S t a t u s r e g i s t e r sAccess instructions Register bitsStatus and domain fields Fault a d d r e s s r e g i s t e rPriority Source Size Status Domain A c h e O p e r a t i o n s r e g i s t e r Function DescriptionFunction/operation Data format Instruction Cache operation functionsMVA Set/Way example Test and clean DCache instructions Modified virtual address format MVA Set/Way formatUnpredictable Test, clean, and invalidate DCache instructionL B O p e r a t i o n s r e g i s t e r Operation Data InstructionCache ways A c h e L o c k d o w n r e g i s t e rModified virtual address format MVA That allows you to control each cache way independentlyInstructions AccessInstruction or data lockdown register Modifying the Cache Lockdown register Register formatFor each of the cache lines to be locked down in cache way Bit Cache unlock procedure0 T L B L o c k d o w n r e g i s t e r Which region the TLB entry is placedProgramming instructions Sample code sequence 1 a n d R 1 2 r e g i s t e r s3 P r o c e s s I D r e g i s t e r Use these instructions to program the TLB Lockdown registerRegister format This is the format of the Fcse PID register Fcse PID register Access instructionsPerforming a fast context switch Function Data ARM instruction4 r e g i s t e r Context ID register Access instructionsAccessing reading or writing this register is reserved 5 T e s t a n d d e b u g r e g i s t e rState space servo control MMU FeaturesM o r y M a n a g e m e n t U n i t M M U Protection schemeAccess permissions and domains Translated entries MMU program accessible registers Address translation Register Bits DescriptionTranslation table base TTB register FormatTable walk process First-level fetchFirst-level descriptor First-level fetch concatenation and addressTable descriptors Bits Section Coarse Fine Description Section descriptor FormatValue Meaning Description Descriptor Section descriptor Bit descriptionFine page table Bits Description113 Second-level descriptor Second-level descriptor format Second-level descriptor pagesSecond-level descriptor least significant bits Second-level descriptor bit assignmentsBits Large Small Tiny Description Translation sequence for large page references Translating sequence for small page references Level descriptor Translation Sequence for tinyReferences More informationU Fault s a n d C P U a b o r t s FAR values for Multi-word Priority encoding table Fault Address register FARDomain Fault Address register TransfersInterpreting access permission bits Compatibility issuesSpecifying access permissions M a i n a c c e s s c o n t r o lFault c h e c k i n g s e q u e n c e Privileged permissions User permissionsNo access 00 Reserved Check domain status Fault checking sequence A b l i n g a n d d i s a b l i n g t h e M M U T e r n a l a b o r t sEnabling B s t r u c t u r e DisablingCache features C h e s a n d w r i t e b u f f e rWrite buffer Enabling the caches R1 register C and M bits for DCache Bit settingsSettings DCacheC h e M V a a n d S e t / W a y f o r m a t s Description ARM926EJ-S behavior Table C Table B BitGeneric, virtually indexed, virtually addressed cache ARM926EJ-S Cache formatFor example, with a 4-way cache a = N c a c h a b l e i n s t r u c t i o n f e t c h e sThis figure Self-modifying codeAHB behavior Instruction Memory Barrier Sample IMB sequences Noncachable instruction fetches Features S i n t e r c o n n e c t i o nS t e m b u s a r b i t e r Master will not occupy the system bus OwnershipUntil the transaction completes Locked bus sequence Relinquishing the busSplit transfers Arbiter configuration example D r e s s d e c o d i n g Address range Size System functionsO g r a m m a b l e t i m e r s Software watchdog timerMaster Name Hmaster30 assignment N e r a l p u r p o s e t i m e r s / c o u n t e r s Gptc characteristics Control fieldSource clock frequency Bit mode options S i c P W M f u n c t i o nA d r a t u r e d e code r f u n c t i o n H a n c e d P W M f u n c t i o nSample enhanced PWM waveform Quadrature Encoding truth Input signalsNC No change CW Clockwise CCW Counter clockwise Err Error CCWMonitors how far the encoder has moved Typical application Testing signalsTimer support Digital filterIRQ interrupts T e r r u p t c o n t r o l l e rFIQ interrupts VectorIRQ characteristics Interrupt sources IRQ FIQInterrupt sources are assigned as shown Interrupt ID Interrupt sourceN f i g u r a b l e s y s t e m a t t r i b u t e s L c o n f i g u r a t i o nConfiguring the powerup settings PLL configuration and control system block diagramO t s t r a p i n i t i a l i z a t i o n Pin name Configuration bits S t e m c o n f i g u r a t i o n r e g i s t e r s Offset 3124 2316 158155 Isaddr System Memory Chip Select 0 Dynamic Memory Mask Address A090 N e r a l a r b i t e r C o n t r o l r e g i s t e rC 0 , B R C 1 , B R C 2 , a n d B R C 3 r e g i s t e r s RegisterChannel allocation Register Register bit assignment B Error D e t e c t S t a t u sChannel enable bit This is how the channels are assigned in the four registersAddress A090 001C EDS1Not reset AHB error response Not reset CPU instruction errorNot reset CPU data error Transaction type write or readM e r M a s t e r C o n t r o l r e g i s t e r AHB Error Interrupt ClearAHB Slave Error Response Detect Config EICTimer 9 high step enable Timer 9 reload step enableTimer 9 low step enable Timer 8 reload step enableM e r 0 4 C o n t r o l r e g i s t e r s Addresses A090 0190 / 0194 / 0198 / 019C / 01A0Debug mode Timer enableCapture and compare mode functions Timer clock selectM e r 5 C o n t r o l r e g i s t e r Address A090 01A4Reload mode TM2M e r 6 9 C o n t r o l r e g i s t e r s Addresses A090 01A8 / 01AC / 01B0 / 01B4D3118 Reserved D1716 M e r 6 9 H i g h r e g i s t e r s M e r 6 9 L o w r e g i s t e r s High step direction M e r 6 9 H i g h a n d L o w S t e p r e g i s t e r sM e r 6 9 R e l o a d S t e p r e g i s t e r s High stepReload step direction Reload stepM e r 0 9 R e a d a n d C a p t u r e r e g i s t e r Interrupt Vector Address register Individual register mappingRegister 3124 2316 1508 0700 Invert Interrupt enableA D D R r e g i s t e r Interrupt typeInterrupt status active Interrupt service routine addressT e r r u p t S t a t u s a c t i v e ISAAddress A090 016C T e r r u p t S t a t u s R a wF t w a r e W a t c h d o g C o n f i g u r a t i o n IsrawF t w a r e W a t c h d o g T i m e r Software watchdog enableSoftware watchdog timer clock select Software watchdog interrupt clearO c k C o n f i g u r a t i o n r e g i s t e r Watchdog timerAddress A090 017C CPU clock select Clock scale controlMax clock scale control Memory clock outIO hub D u l e R e s e t r e g i s t e rEthernet MAC RST Stat Module Reset register resets each module on the AHB busReset status I2CMiscellaneous System Configuration and Status register Misaligned bus address response mode Boot modeEndian mode Internal register access mode bitPLL frequency formula Register Register bit assignment L C o n f i g u r a t i o n r e g i s t e rPLL bypass Intid W e r M a n a g e m e n tAddress A090 018C Interrupt IDHardware clock scale control Deprecated Chip sleep enableNew designs should not use this bit Sdram self refresh controlI2C wakeup CPU wake interrupt clearRTC wakeup SPI wakeupAddress A090 022C B B u s a c t i v i t y S t a t u sAddresses A090 01D0 / 01D4 Addresses A090 01D8 / 01DC Chip select 0 disableRegisters Chip select 0 baseAddresses A090 01E0 / 01E4 Chip select 1disableChip select 1 base Addresses A090 01E8 / 01EC Chip select 2 disableChip select 2 base Addresses A090 01F0 / 01F4 Chip select 3 disableChip select 3 base Addresses A09001F8 / 01FC Chip select 0 maskChip select 1 disable Addresses A090 0200Addresses A090 0208 / 020C N I D r e g i s t e r Status GenidSTS CLRRTC Module Control register controls the RTC module RTC standby mode statusC M o d u l e C o n t r o l r e g i s t e r PolarityRTC module interrupt status RTC standby modeRTC clock ready interrupt status RTC clock ready interrupt clearRTC Module Control register Static memory features, such as Memory controller provides these featuresWith and without asynchronous page mode Amba 32-bit AHB compliancyW p o w e r o p e r a t i o n Power-on reset memory map M o r y m a pExample Boot from flash Sdram remapped after boot ROM Device Write protect Mode BufferA t i c m e m o r y c o n t r o l l e r SramWrite protection Extended wait transfers Be awareA t i c m e m o r y i n i t i a l i z a t i o n Access sequencing and memory width Wait state generationMemory mapped peripherals A t i c m e m o r y r e a d c o n t r o l Programmable enableOutput enable programmable delay ROM, SRAM, and FlashTiming parameter Value External memory read transfer with zero wait statesExternal memory read transfer with two wait states WAITRD2 WAITOEN0 WAITPAGEN/A WAITWRN/AExternal memory read transfers with zero wait states WAITENN/A WAITTURNN/ABurst of zero wait states with fixed length Burst of two wait states with fixed lengthExternal memory page mode read transfer Y n c h r o n o u s p a g e m o d e r e a dTiming parameters Value External memory 32-bit burst read from 8-bit memoryWAITRD2 WAITOEN0 WAITPAGE1 WAITWRN/A WAITWENN/A WAITTURNN/A WAITRD0 WAITOEN0 WAITPAGE0 WAITWRN/A WAITWENN/A WAITTURNN/AWait states added between external read and write transfers Write enable programming delayA t i c m e m o r y w r i t e c o n t r o l External memory write transfer with zero wait statesExternal memory write transfer with two wait states WAITRDN/A WAITOENN/A WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN0 Read followed by write with no turnaround S t u r n a r o u n dS t u r n a r o u n d T i m i n g a n d p a r a m e t e r s WAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN0Write followed by a read with no turnaround Read followed by a write with two turnaround cyclesT e l a n e c o n t r o l WAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN2D r e s s c o n n e c t i v i t y Memory banks constructed from 16-or 32-bit memory devices Memory banks constructed from 16-bit memory2Mx32 ROM N a m i c m e m o r y c o n t r o l l e r Access sequencing and memory widthR a M I n i t i a l i z a t i o n Left-shift value -bit wide data bus Sdram RBC Device size Configuration Load Mode register left shiftBit Parameter Parameter description 256M 8M x 16M x 32M x 512M 64M x Device Signal Bit wide ConfigurationSignal 16M device 64M device 128M 256M 512M Left-shift value -bit wide data bus Sdram BRCBA0 BA1Only. Bursting is not allowed G i s t e r sRegister map Address Register DescriptionTRWL, tRDL N t r o l r e g i s t e r Reset valuesAddress A070 Memory controller enable Bits Access Mnemonic DescriptionLow-power mode Address mirrorSelf-refresh acknowledge Srefack A t u s r e g i s t e rN f i g u r a t i o n r e g i s t e r Write buffer statusN a m i c M e m o r y C o n t r o l r e g i s t e r ENDSdram initialization Sync/Flash reset/power down signal dypwrnDynamic memory clock enable Self-refresh request SrefreqRefresh timer RefreshRead data strategy Active to precharge command period tRAS Precharge command period tRPRAS Srex Address A070 003CSelf-refresh exit time tSREX Last-data-out to active command time tAPR APRData-in to active command tDAL or tAPW DALActive to active command period tRC Address A070 004CRFC Auto-refresh period and auto-refresh to active commandPeriod Exit self-refresh to active time command XSRActive Bank a to Active Bank B Load mode register to Active Command TimeRRD MRDExample External wait timeoutA t i c M e m o r y E x t e n d e d W a i t r e g i s t e r Address A070 0100 / 0120 / 0140Address mapping Write protectBdmc AM1For the Dynamic Memory ConfigurationAddress mapping 119 DescriptionAddress A070 0104 / 0124 / 0144 For a chip select connected to Select this mappingCAS latency RAS latency active to read/write delayCAS Do not modifyBsmc Buffer enablePsmc Extended waitChip select polarity Byte lane stateMode Bmode Burst modeMemory width Address A070 0208 / 0228 / 0248 Wait write enable WaitwenWait output enable Waitoen WwenA t i c M e m o r y R e a d D e l a y 0 3 r e g i s t e r s Nonpage mode read wait states or asynchronous page modeRead first access wait state Waitrd WtrdAsynchronous page mode read after the first wait state WtpgWtwr Address A070 0218 / 0238 / 0258Write wait states Waitwr Wttn Bus turnaround cycles WaitturnStaticMemory Turn Round Delay 0-3 registers Features Common acronyms Ethernet Communication ModuleH e r n e t M a C Ethernet communications moduleMAC module block diagram Features Feature DescriptionStation address logic A t i o n a d d r e s s l o g i c S a LPHY interface mappings Media Independent InterfaceA t i s t i c s m o d u l e MAC receiverEthernet front- end module EFE H e r n e t f r o n t e n d m o d u l eReceive packet processor C e i v e p a c k e t p r o c e s s o r Transmit packet processorReceive buffer descriptor format Transferring a frame to system memoryReceive buffer descriptor format description A n s m i t p a c k e t p r o c e s s o r Receive buffer descriptor field definitionsTransmit buffer Descriptor field Transmit buffer descriptor formatDefinitions Transmitting a frame Successfully FrameTransmitted UnsuccessfullyT e r r u p t s H e r n e t s l a v e i n t e r f a c eInterrupt condition Description S e t s Bit field Register Active Default Modules reset StateStatus bits Multicast address Filter registers L t i c a s t a d d r e s s f i l t e r i n gFilter entries Multicast address filtering exampleFiltering example O c k s y n c h r o n i z a t i o nMulticast address Writing to other registersRegister address Filter Eintren RxdptrEintr TxptrH e r n e t G e n e r a l C o n t r o l R e g i s t e r # Address A060Enable TX packet processing Enable RX packet processingEnable receive DMA Accept short 64 receive framesEtxdma Enable transmit DMAEnable initialization of RX buffer descriptors ErxinitAlign RX data MAC host interface soft resetRX Fifo RAM access Insert transmit source addressH e r n e t G e n e r a l S t a t u s r e g i s t e r Rxinit H e r n e t T r a n s m i t S t a t u s r e g i s t e rRX initialization complete Multicast frame transmitted Frame transmitted OKBroadcast frame transmitted TX abort late collisionH e r n e t R e c e i v e S t a t u s r e g i s t e r Address A060 001CReceive broadcast frame Receive frame size in bytesReceive frame OK Receive multicast frameC C o n f i g u r a t i o n R e g i s t e r # Internal loopback Receive enableBits Access Mnemonic Reset Definition Excess deferralPad/CRC enable Auto detect pad enableVlan pad enable CRC enableFrames C k t o B a c k I n t e r P a c k e t G a p r e g i s t e rPAD operation Table for transmit TypeAddress A060 040C Full-duplex modeHalf-duplex mode Back-to-back inter-packet-gapIPGR1 L l i s i o n W i n d o w / R e t r y r e g i s t e rAddress A060 Non back-to-back inter-packet-gap partCollision window X i m u m F r a m e r e g i s t e rCwin RetxMaximum frame length Reset MII management blockRmiim Clock select Clocks field SettingsI M a n a g e m e n t C o m m a n d r e g i s t e r Suppress preambleIf both Scan and Read are set, Scan takes precedence I M a n a g e m e n t a d d r e s s r e g i s t e rRegister bit Automatically scan for read dataI M a n a g e m e n t R e a d D a t a r e g i s t e r I M a n a g e m e n t W r i t e D a t a r e g i s t e rAddress A060 042C Miilf I M a n a g e m e n t I n d i c a t o r s r e g i s t e rMII read data MII link failureNvalid A t i o n a d d r e s s r e g i s t e r sRead data not valid Automatically scan for read data in progressStation Address Register #1 A t i o n a d d r e s s F i l t e r r e g i s t e rRegister bit assignments for all three registers Station Address Register #2PRM G i s t e r H a s h T a b l e sPRO PRAAddress Register Transmit and receive counters A t i s t i c s r e g i s t e r sTR1K Receive packet counter A060 06A0 Receive statistics Counters addressReceive byte counter A060 069C Address Register Receive countersReceive broadcast packet counter A060 06AC Receive FCS error counter A060 06A4Receive multicast packet counter A060 06A8 RbuoReceive carrier sense error counter A060 06C8 Receive alignment error counter A060 06BCReceive code error counter A060 06C4 Receive undersize packet counter A060 06CCTransmit byte counter A060 06E0 Receive jabber counter A060 06D8Transmit statistics counters address map Address Register Transmit countersTransmit packet counter A060 06E4 Transmit excessive collision packet counter A060 These are the General Statistics registers Transmit oversize frame counter A060Transmit undersize frame counter A060 Carry RegisterC1RBY C1MAXC1MGV C1RPKMask register M1RPK M1MGVM1RBY M1RFCAddress A060 073C Mask register Register0x00000000 RXA Buffer Descriptor Pointer Address A060 0A04RXB Buffer Descriptor Pointer RXC Buffer Descriptor Pointer Address A060 0A08Address A060 0A0C RXD Buffer Descriptor PointerRxovflstat H e r n e t I n t e r r u p t S t a t u s r e g i s t e rAddress A060 0A10 RxbufcRxdoned RxdonebRxdonec RxnobufH e r n e t I n t e r r u p t E n a b l e r e g i s t e r Address A060 0A14Address A060 0A18 Address A060 0A1C Address A060 0A20Address A060 0A24 Address A060 0A28 Address A060 0A2C Address A060 0A30Address A060 0A34 Address A060 0A38Rxfreed F r e e B u f f e r r e g i s t e rAddress A060 0A3C RxfreecL t i c a s t a d d r e s s F i l t e r r e g i s t e r s Address A060 0A60 Address A060 0A58Address A060 0A5C Address A060 0A64L t i c a s t a d d r e s s M a s k r e g i s t e r s Address A060 0A98 Address A060 0A90Address A060 0A94 Address A060 0A9CAddress A060 0ABC Address A060 0AB4Address A060 0AB8 Address A060 0AC0B u f f e r D e s c r i p t o r R a M Offset+0Offset+C Offset+4Offset+8 Address A060 2000 512 locationsM p l e h a s h t a b l e code Pointer to buffer to store hash table Pointer to hash table 337 Sample hash table code External DMA A t r a n s f e r sSource address pointer Buffer length DMA buffer descriptor diagramA b u f f e r d e s c r i p t o r DestinationS c r i p t o r l i s t p r o c e s s i n g Determining the width of Pden Equation variables Use this equation to compute total access timeR i p h e r a l D M a r e a d a c c e s s Variable DefinitionPeripheral DMA burst read access Peripheral DMA single read accessR i p h e r a l D M a w r i t e a c c e s s REQ signal Peripheral DMA burst write accessREQ signal Logic remains paused until the REQ signal is reassertedA t i c R a M c h i p s e l e c t c o n f i g u r a t i o n Done signal Special circumstancesStatic ram chip select configuration Register name Field Value CommentA B u f f e r D e s c r i p t o r P o i n t e r A C o n t r o l r e g i s t e r Source width Channel enableChannel go Destination widthDestination burst Fly-by modeSource address increment State ResetIndex Buffer not ready interrupt pending Error completion interrupt pendingNormal completion interrupt pending Channel abort interrupt pendingA P e r i p h e r a l C h i p S e l e c t r e g i s t e r SEL Chip selectDMA Peripheral Chip Select register Is programmable for 128-, 192-, or 256-bit key lengths AESProcesses 32 bits at a time Supports ECB, CBC, OFB, CTR, and CCM cipher modesS D M a b u f f e r d e s c r i p t o r Block diagramKey size Characteristic 128 192 256 Data blocksSource buffer length AES buffer descriptor diagramSource address pointer Destination buffer lengthAES op code Interrupt I bit Last L bit Full F bitC r y p t i o n B p r o c e s s i n gC , C F B , O F B , a n d C T R p r o c e s s i n g CCM mode does not require an initialization vectorM m o d e Nonce buffer ContentsBits CCM mode Hub Module Interface A c o n t r o l l e rAHB slave Servicing RX and FIFOsControl13 L Source address pointer Buffer length Control15 WControl14 Control12 FControl110 Status150Process A n s m i t D M a e x a m p l eNot applicable Pointer and IndexVisual example System MemoryUart B register Address map ReservedUart a register Address map Register Offset DescriptionUart C register Address map Uart D register Address mapReserved SPI register Address mapAD register Address map I2C register Address mapIO Hardware Assist register RTC register Address mapIO register Address map Buffer not ready interrupt pending RX Error completion interrupt pending RXNormal completion interrupt pending RX Channel abort interrupt pending RXTX Fifo service request interrupt pending RX Fifo service request interrupt pendingError completion interrupt pending TX RX Fifo overflow interrupt pendingD u l e D M a R X C o n t r o l Flex I/O Channel abortDirect Rxthrs RxbdpRX Fifo threshold D u l e D i r e c t M o d e R X S t a t u s F I F O D u l e D i r e c t M o d e R X D a t a F I F O Full flagD u l e D M a T X C o n t r o l IndexenTxbdp D u l e D i r e c t M o d e T X D a t a F I F O TX Fifo thresholdTXD D u l e D i r e c t M o d e T X D a t a L a s t F I F OTxdl 384 Character gap timeout Modem control signal supportReceive error conditions DMA transfers to and from system memoryUart module structure Example configurationR m a l m o d e o p e r a t i o n Control register Field Value CommentThis table shows the baud rates achieved with CLKref set to U d r a t e g e n e r a t o rBaud rates Divisor Baud rateR d w a r e b a s e d f l o w c o n t r o l R c e d c h a r a c t e r t r a n s m i s s i o nForce character transmission procedure Collecting feedback M w a k e u p o n c h a r a c t e r r e c o g n i t i o nDLAB=0 A p p e r C o n t r o l a n d S t a t u s r e g i s t e r sAddress Register DLAB=1RTS A p p e r C o n f i g u r a t i o n r e g i s t e rRtsen DtrenRemote loopback SoftwareReceive character-based flow control RTS controlRS485 transceiver deassertion control Enable force completeT e r r u p t E n a b l e r e g i s t e r RS485 transceiver assertion controlEnable frame error Enable overflow errorEnable parity error Enable line breakT e r r u p t S t a t u s r e g i s t e r Uart interrupt Parity errorFrame error Force completeCharacter match2 Ring indicatorCharacter match3 Character match1Receive idle Enable receive character gap timerTransmit idle Write this field toEnable transmit bit rate generation C e i v e B u f f e r G a P C o n t r o l r e g i s t e rMask Enable character matchData Flow control state Flow control enableFlowstate FLOW4FLOW2 Read-only busy Force transmit enableM W a k e u p C o n t r o l r e g i s t e r CharAddress 90011034 / 90019034 / 90021034 EnableA n s m i t B y t e C o u n t TxcountR T T r a n s m i t B u f f e r R T R e c e i v e B u f f e rRbuff Tbuff R T B a u d R a t e D i v i s o r L S BR T B a u d R a t e D i v i s o r M S B BrdlBrdm Enables modem status interruptR T I n t e r r u p t E n a b l e r e g i s t e r EdssiEnables receive data available interrupt Enables receive line status interruptEnables transmit holding register empty interrupt Interrupt identificationR T L i n e C o n t r o l r e g i s t e r Enable the TX and RX FifoR T F I F O C o n t r o l r e g i s t e r Clear all bytes in the TX FifoSet break, if set TX data is set to Divisor latch access bitParity enable Stick parity, operates as followsR T L i n e S t a t u s r e g i s t e r Local loopback enable bitR T M o d e m C o n t r o l r e g i s t e r Automatic flow controlR T M o d e m S t a t u s r e g i s t e r Delta DSR indicator Delta DCD indicatorTrailing edge of RI indicator Delta CTS indicatorUart Modem Status register C e i v e a n d t r a n s m i t o p e r a t i o n s Hdlc module structureTransmit operation O c k i n gT s Transmitter underflowEncoding examples T a e n c o d i n gLast byte bit Pattern table Last byte bit pattern Valid dataTransitions Dpll operation Adjustment ranges and output clocks NRZ and Nrzi encoding Biphase-Level encoding CLK Address Received or a buffer close event occurs, such as end Enable valid CRC Enable Hdlc interruptEnable invalid CRC Local loopbackEnable receive abort error RabortInvalid CRC Receive abort errorHdlc interrupt Valid CRCL C D a t a R e g i s t e r HdataHdata Hmode L C C o n t r o l R e g i s t e rClock source L C C l o c k D i v i d e r L o w Address 9002911C L C C l o c k D i v i d e r H i g hDivl Clock enable DivhMaster mode internal diagnostic loopback Four-wire interface RXD, TXD, CLK, CSProgrammable SPI mode 0, 1, 2, or Interface SPI moduleI c o n t r o l l e r SPI module structureI c l o c k i n g m o d e s Timing modes Clocking mode diagramsSPI mode SPI CLK Idle Capture edge Drive edgeS t e m b o o t o v e r S P I o p e r a t i o n SPI master mode SPI slave modeI c l o c k g e n e r a t i o n Clock generation samplesEEPROM/FLASH header Bootmode10 Address widthAvailable Strapping options Entry NameTime to completion Entry Name DescriptionEnable master loopback mode Configuration registers for the SPI module are located atThis is the primary SPI Configuration register I C o n t r o l a n d S t a t u s r e g i s t e r sO c k G e n e r a t i o n r e g i s t e r SPI modeSlave enable Discard bytesRegister programming steps Bits Access Mnemonic Reset DivisorEnable clock generation Use this register to define the data rate of the interfaceD3102 Not used Write this field to D01 SPI master timing Parameters I t i m i n g c h a r a c t e r i s t i c sParm Description Min Max Unit SPI master timing diagram SPI slave timing parameters SPI slave timing diagram SPI timing characteristics I2C bus Interface timing, data structure, and error handlingY s i c a l I 2 C b u s OverviewE x t e r n a l a d d r e s s e s Slave Description Addres BitCommand Name Description C o m m a n d i n t e r f a c eAddress 9005 R e g i s t e r sM m a n d T r a n s m i t D a t a r e g i s t e r RegisterDescription2C Dlen port iicdlen A t u s R e c e i v e D a t a r e g i s t e rProvide new transmit data Mcmdl S t e r a d d r e s s r e g i s t e rScmdl IrqcdA v e a d d r e s s r e g i s t e r Timing parameter for fast-mode Register Address 9005 000CMask the interrupt to the ARM CPU irqdis Master/slave interrupt codes T e r r u p t codesCode Name Master/slave Description F t w a r e d r i v e r I2C master software driver I2C slave high level driverO w c h a r t s Master module normal mode, 16- bitSlave module normal mode, 16- bit Real Time Clock Module C G e n e r a l C o n t r o l r e g i s t e r Address 9006Calendar operation 12/24 clock mode operation2 4 H o u r r e g i s t e r Time date, hour, minute, second operationHRT M e r e g i s t e rHRU L e n d a r r e g i s t e r Address 9006 000CM e Alarm r e g i s t e r L e n d a r Alarm r e g i s t e r Alarm E n a b l e r e g i s t e rE n t F l a g s r e g i s t e r Address 9006 001CDate event Alarm eventMonth event Hour eventDate interrupt Alarm interruptMonth interrupt Hour interruptT e r r u p t D i s a b l e r e g i s t e r T e r r u p t E n a b l e S t a t u s r e g i s t e r N e r a l S t a t u s r e g i s t e r Address 9006 002CGeneral Status register ADC module StructureC D M a p r o c e d u r e ADC control blockC c o n t r o l a n d s t a t u s r e g i s t e r s ADC configuration registers are located at offsetC C o n f i g u r a t i o n r e g i s t e r Interrupt status DMA enableADC channel select C O u t p u t R e g i s t e r s 0 C C l o c k C o n f i g u r a t i o n r e g i s t e rWait Dout E c t r i c a l c h a r a c t e r i s t i c s Parameter Symbola Rating UnitAbsolute maximum ratings CPU / Memory clock Power Parameter Symbol a Rating UnitRecommended operating conditions Inputs E l e c t r i c a l c h a r a c t e r i s t i c sSym Parameter Conditiona Value Unit Ouputs Sym Parameter Value Unit74LVC1G17GW Manufacturer Part Number DescriptionNC7SP17 SN74LVC1G17DCM o r y T i m i n g Sdram burst read 16-bit Sdram burst read 16 bit, CAS latency = Sdram burst write 16 bit Sdram burst read 32 bit Sdram burst read 32 bit, CAS latency = Sdram burst write 32-bit Sdram load mode Sdram refresh mode Clock enable timing Parm Description Min Max Unit Static RAM read cycles with 0 wait states Static RAM asynchronous page mode read, Wtpg = Static RAM read cycle with configurable wait states Static RAM sequential write cycles Static RAM write cycle Static write cycle with configurable wait states Slow peripheral acknowledge timing CPUSlow peripheral acknowledge read Slow peripheral acknowledge writeEthernet timing Ethernet MII timingStandard Mode Fast Mode Parm Description Min Max Unit I2C timingSPI master parameters SPI TimingParm Description Min Max Unit Mod Not SPI slave parametersTbclk *8 SPI master mode 0 and 1 2-byte transfer SPI master mode2 and 3 2-byte transferSPI slave mode 0 and 1 2-byte transfer SPI slave mode 2 and 3 2-byte transferS e t a n d h a r d w a r e s t r a p p i n g t i m i n g Parm Description Min Typ UnitA G t i m i n g O c k t i m i n g Diagram below pertains to clock timingSystem PLL reference clock Timing Clock timing Packaging C k a g eO c e s s o r D i m e n s i o n s C K a G I N G Processor Dimensions V i s i o n B V i s i o n C