NRZ and Nrzi encoding Biphase-Level encoding

S E R I A L C O N T RO L M O D U L E : H D L C

DPLL operation: Adjustment ranges and output clocks

Bit cell

NRZI adj

NRZI Clock

Bi-L adj

Bi-L Clock

Bi-S adj

Bi-S Clock

Bi-Madj

Bi-MClock

none

add one

ignore transitions

add one

add two

subtract one

none

ignore transitions

subtract two

add one

subtract one

ignore transitions

subtract one

none

NRZ and NRZI encoding

Biphase-Level encoding

With NRZ and NRZI encoding, all transitions occur on bit-cell boundaries and the data should be sampled in the middle of the bit cell.

If a transition occurs after the expected bit-cell boundary, but before the midpoint, the DPLL needs to lengthen the count to line up the bit-cell boundaries; this corresponds to the “add one” and “add two” regions of the figure.

If a transition occurs before the bit-cell boundary, but after the midpoint, the DPLL needs to shorten the count to line up the bit-cell boundaries; this corresponds to the “subtract one” and “subtract two” regions shown in the figure.

The DPLL makes no adjustment if the bit-cell boundaries are lined up within one count of the divide-by-sixteen counter. The regions that adjust the count by two allow the DPLL to synchronize faster to the data stream when starting up.

With biphase-level encoding, there is a guaranteed “clock” transition at the center of every bit-cell and optional “data” transitions at the bit-cell boundaries. The DPLL

420Hardware Reference NS9215

NS9215 specifications

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Digi NS9215 manual NRZ and Nrzi encoding Biphase-Level encoding

Models: NS9215

DPLL operation: Adjustment ranges and output clocks

NRZ and NRZI encoding

Biphase-Level encoding

420Hardware Reference NS9215

NS9215 specifications