O n t r o l r e g i s t e r, Size field Cache size

WO R K I N G W I T H T H E C P U

R1: Control register

Field	Description

Size	Determines the cache size in conjunction with the M bit.
	The M bit is 0 for DCache and ICache.
	The size field is bits [21:18] for the DCache and bits [9:6] for the ICache.
	The minimum size of each cache is 4 KB; the maximum size is 128 KB.
	Cache size encoding with M=0:
	Size field		Cache size
	0b0011		4 KB
	0b0100		8 KB
	Note:	The processor always reports 4KB for DCache and 8KB for ICache.

Assoc	Determines the cache associativity in conjunction with the M bit.
	The M bit is 0 for both DCache and ICache.
	The assoc field is bits [17:15 for the DCache and bits [5:3] for the ICache.
	Cache associativity with encoding:
	Assoc field		Associativity
	0b010		4-way
	Other values		Reserved

M bit	Multiplier bit. Determines the cache size and cache associativity values in conjunction with
	the size and assoc fields.
	Note:	This field must be set to 0 for the ARM926EJ-S processor.

Len	Determines the line length of the cache.
	The len field is bits [13:12] for the DCache and bits [1:0] for the ICache.
	Line length encoding:
	Len field		Cache line length
	10		8 words (32 bytes)
	Other values		Reserved

R 1 : C o n t r o l r e g i s t e r

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Register R1 is the control register for the ARM926EJ-S processor. This register specifies the configuration used to enable and disable the caches and MMU (memory management unit). It is recommended that you access this register using a read- modify-write sequence.

For both reading and writing, the CRm and opcode_2 fields SHOULD BE ZERO. Use these instructions to read and write this register:

MRC p15, 0, Rd, c1, c0, 0; read control register

MCR p15, Rd, c1, c0, 0; write control register

All defined control bits are set to zero on reset except the V bit and B bit. The V bit is set to zero at reset if the VINITHI signal is low.

The B bit is set to zero at reset if the BIGENDINIT signal is low, and set to one if the BIGENDINIT signal is high.

88Hardware Reference NS9215

NS9215 specifications

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Digi NS9215 manual O n t r o l r e g i s t e r, Size field Cache size, Assoc field Associativity

Models: NS9215

Field

Size field

Cache size

Assoc field

Associativity

Len field

Cache line length

R 1 : C o n t r o l r e g i s t e r

88Hardware Reference NS9215

NS9215 specifications