H e r n e t f r o n t e n d m o d u l e

E T H E R N E T C O M M U N I C A T I O N M O D U L E

Ethernet front-end module

The counters support a clear on read capability that is enabled when AUTOZ is set to 1 in the Ethernet General Control Register #2.

E t h e r n e t f r o n t - e n d m o d u l e

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ethernet front- end module (EFE)

Ethernet MAC

MAC Host I/F, Stat Host I/F, SAL Host I/F

System Cfg

To Receive/Transmit

AHB

Packet Processors

Control Registers

Slave

Interface

Status Registers

From

Receive/Transmit Packet Processors

RX Interrupt, TX Interrupt

Rx_frame

Receive Packet Processor

SAL Accept/Reject

Rx Status

RX_WR

RX _RD

AHB

-AHB User I/F

-Src Addr Filter

Rx Ctl

-FIFO WR Ctl

-DMA Pointers

-FIFO RD Ctl

AHB

Rx Data

RX Data FIFO

8:32

2KB

Master

RX Status FIFO

RD Data

Interface

32 entry

Transmit Packet Processor

Tx Status

TX_RD

TX_WR

TX-Buffer

Tx Ctl

-AHB User I/F

Descriptor

-MAC TX Ctl

-FIFO WR Ctl

Ram

-FIFO RD Ctl

-RAM Ctl

64 entries

SA and CTL

WR Ctl

AHB

Mux

TX FIFO

WR Data

Tx Data

32:8

256 Bytes

Master

Interface

Receive packet processor

The EFE module includes a set of control and status registers, a receive packet processor, and a transmit packet processor. On one side, the Ethernet front end interfaces to the MAC and provides all control and status signals required by the MAC. On the other side, the Ethernet front end interfaces to the system.

The receive packet processor accepts good Ethernet frames (for example, valid checksum and size) from the Ethernet MAC and commits them to external system memory. Bad frames (for example, invalid checksum or code violation) and frames with unacceptable destination addresses are discarded.

266Hardware Reference NS9215

Page 266

Image 266

Digi NS9215 manual H e r n e t f r o n t e n d m o d u l e, Ethernet front- end module EFE, Receive packet processor

NS9215 specifications

The Digi NS9215 is a powerful solution designed for industrial applications that require reliable connectivity and robust performance. Built on a foundation of advanced technologies, the NS9215 serves as a versatile networking device that meets the demands of automation, remote monitoring, and data acquisition.

One of the standout features of the Digi NS9215 is its multi-protocol support. It is capable of handling various communication protocols, including Ethernet, Serial, and Wireless, making it ideal for integration into heterogeneous environments. This flexibility enables users to connect legacy devices to modern networks seamlessly, facilitating smoother data communication across different platforms.

The NS9215 is equipped with powerful processing capabilities, featuring an integrated processor that ensures efficient data handling. This enables the device to perform complex data tasks without compromising performance. Its high-speed connectivity options also allow for rapid data transmission, which is crucial for real-time applications in industrial settings.

Another critical characteristic of the Digi NS9215 is its reliability in harsh environments. Built to withstand extreme temperatures, humidity, and electrical interference, this device assures consistent operation even in challenging conditions. Its rugged design minimizes the risk of failure, making it suitable for deployment in various industrial environments.

Security is a top priority for the Digi NS9215. It comes with advanced security features that protect sensitive data during transmission and prevent unauthorized access. Employing encryption protocols and secure authentication methods, the NS9215 ensures that data integrity and confidentiality are maintained throughout its operation.

The user-friendly interface of the NS9215 allows for easy configuration and management. This ease of use reduces the time required for installation and setup, enabling quick deployment in field operations. Additionally, remote management capabilities enhance operational efficiency, allowing users to monitor device performance and make adjustments from anywhere.

Furthermore, the NS9215 supports extensive scalability options. As organizations grow and evolve, the ability to scale up or adapt the networking capabilities becomes essential. With its modular design, the NS9215 can easily accommodate additional devices and protocols, ensuring longevity and continued relevance in a rapidly changing technological landscape.

In conclusion, the Digi NS9215 is a robust networking device designed for a wide range of industrial applications. Its multi-protocol support, reliability, security features, user-friendly interface, and scalability make it a valuable addition to any industrial network infrastructure, delivering performance and efficiency that businesses can depend on for critical operations.

Contents

NS9215 Hardware Reference 90000847C Release date 10 AprilPage Page Page Contents A p t e r 3 W o r k i n g w i t h t h e C P U 102 105 A p t e r 4 S y s t e m C o n t r o l M o d u l e 137 141 A p t e r 5 M e m o r y C o n t r o l l e r 203 Sram Bit wide configuration 228 229 Hardware Reference NS9215 HT1 315 A p t e r 7 E x t e r n a l D M a 339 Hardware Reference NS9215 A p t e r 9 I / O H u b M o d u l e 363 Hardware Reference NS9215 A p t e r 1 1 S e r i a l C o n t r o l D u l e H D L C 415 Hardware Reference NS9215 A p t e r 1 4 R e a l T i m e C l o c k M o d u l e 459 A p t e r 1 6 T i m i n g 479 A p t e r 1 7 P a c k a g i n g 513 Hardware Reference NS9215 Pinout Heading Description Pin Signal Description M o r y b u s i n t e r f a c e N O U T 2 6 Sdram RAS Pin SignalH e r n e t i n t e r f a c e M a C Sdram CAS N e r a l p u r p o s e I / O G P I O DSR Uart a DCD Uart aCTS Uart a RXD Uart a I2C SCL DCD / TXC Uart CCTS Uart C Picdbgdataini DSR Uart B DCD Uart BCTS Uart B RXD Uart B RI Uart D DSR Uart DRXD Uart D TXC / DTR Uart D Pin Signal Description PIC1CLKI PIC1CLKO Pin Signal Description PIC0CLKI PIC0CLKO Pin Signal Description Pin Signal Description Pin Signal Description S t e m c l o c k I/O OD System clock drawing RTC clock and battery backup drawing S t e m m o d e Sysmode2 Sysmode1 Sysmode0 Description S t e m r e s e t SPI YES A G T e s t Adcvss R a n d b a t t e r y b a c k e d l o g i c POR VSS W e r a n d g r o u n d GND Power and ground System memory bus I/O control Address Description Access Reset valueN t r o l a n d S t a t u s r e g i s t e r s Register address Map Control and Status registers Bits Mnemonic Description Gpio configuration optionsI O C o n f i g u r a t i o n r e g i s t e r s Bits Access Mnemonic Reset Description Configuration Register #0Configuration Register #1 Address A0902000 Address A0902008 Configuration Register #2Configuration Register #3 Address A090200C Address A0902010 Configuration Register #4Configuration Register #5 Address A0902014 Address A0902018 Configuration Register #6Configuration Register #7 Address A090201C Address A0902020 Configuration Register #8Configuration Register #9 Address A0902024 Address A0902028 Configuration Register #10Configuration Register #11 Address A090202C Address A0902030 Configuration Register #12Configuration Register #13 Address A0902034 Address A0902038 Configuration Register #14Configuration Register #15 Address A090203C Address A0902040 Configuration Register #16Configuration Register #17 Address A0902044 Address A0902048 Configuration Register #18Configuration Register #19 Address A090204C Address A0902050 Configuration Register #20Configuration Register #21 Address A0902054 Address A0902058 Configuration Register #22Configuration Register #23 Address A090205C Address A0902060 Configuration Register #24Configuration Register #25 GPIOAddress A0902064 Configuration Register #26 Address A0902068 Address A090206C I O C o n t r o l r e g i s t e r sGpio Control Address A0902070 Address A0902074 Address A0902078 Address A0902080 I O S t a t u s r e g i s t e r sGpio Status Address A0902084 Address A090208C M o r y B u s C o n f i g u r a t i o n r e g i s t e rAddress A0902088 CS2 CS0CS1 CS3 High data bus pullup control Apudis Memory Bus Configuration register Working with the CPU About the processor Arm926EJ-S Process block DiagramS t r u c t i o n s e t s ARM instruction set Thumb instruction set ARM926EJ-S system addresses Address manipulation example Accessing CP15 registersJava instruction set Term Abbreviation Description Terms and abbreviationsMnemonics for these instructions are For reads Register Reads Writes Be ZERO, does not cause any physical damage to the chipRegister summary TLB R0 ID code This is the contents of the ID code registerWriting to register R0 is Unpredictable Any value other than 1 or 2. Note this example Field contains these bits Cache type register and field descriptionDsize and Isize fields Field Description Assoc field Associativity O n t r o l r e g i s t e rSize field Cache size Len field Cache line length Bits Name Function Control registerBit functionality Cache ICacheDCache behavior Behavior R a n s l a t i o n T a b l e B a s e r e g i s t e r CRm and opcode2 fields should be Zero when writing to R2Access permissions and instructions O m a i n a c c e s s C o n t r o l r e g i s t e r E g i s t e r Fault S t a t u s r e g i s t e r sAccess instructions Register bits Priority Source Size Status Domain Fault a d d r e s s r e g i s t e rStatus and domain fields A c h e O p e r a t i o n s r e g i s t e r Function Description MVA Cache operation functionsFunction/operation Data format Instruction Set/Way example Test and clean DCache instructions Modified virtual address format MVA Set/Way format Unpredictable Test, clean, and invalidate DCache instructionL B O p e r a t i o n s r e g i s t e r Operation Data Instruction Cache ways A c h e L o c k d o w n r e g i s t e rModified virtual address format MVA That allows you to control each cache way independently Instructions AccessInstruction or data lockdown register Modifying the Cache Lockdown register Register format For each of the cache lines to be locked down in cache way Bit Cache unlock procedure0 T L B L o c k d o w n r e g i s t e r Which region the TLB entry is placed Programming instructions Sample code sequence 1 a n d R 1 2 r e g i s t e r s3 P r o c e s s I D r e g i s t e r Use these instructions to program the TLB Lockdown register Register format This is the format of the Fcse PID register Fcse PID register Access instructionsPerforming a fast context switch Function Data ARM instruction 4 r e g i s t e r Context ID register Access instructionsAccessing reading or writing this register is reserved 5 T e s t a n d d e b u g r e g i s t e r State space servo control MMU FeaturesM o r y M a n a g e m e n t U n i t M M U Protection scheme Access permissions and domains Translated entries MMU program accessible registers Address translation Register Bits Description Translation table base TTB register Format Table walk process First-level fetch Table descriptors First-level fetch concatenation and addressFirst-level descriptor Value Meaning Description Section descriptor FormatBits Section Coarse Fine Description Descriptor Section descriptor Bit descriptionFine page table Bits Description 113 Second-level descriptor Second-level descriptor format Second-level descriptor pages Bits Large Small Tiny Description Second-level descriptor bit assignmentsSecond-level descriptor least significant bits Translation sequence for large page references Translating sequence for small page references Level descriptor Translation Sequence for tinyReferences More information U Fault s a n d C P U a b o r t s FAR values for Multi-word Priority encoding table Fault Address register FARDomain Fault Address register Transfers Interpreting access permission bits Compatibility issuesSpecifying access permissions M a i n a c c e s s c o n t r o l Fault c h e c k i n g s e q u e n c e Privileged permissions User permissions No access 00 Reserved Check domain status Fault checking sequence Enabling T e r n a l a b o r t sA b l i n g a n d d i s a b l i n g t h e M M U B s t r u c t u r e Disabling Cache features C h e s a n d w r i t e b u f f e r Write buffer Enabling the caches R1 register C and M bits for DCache Bit settingsSettings DCache C h e M V a a n d S e t / W a y f o r m a t s Description ARM926EJ-S behavior Table C Table B Bit Generic, virtually indexed, virtually addressed cache ARM926EJ-S Cache format For example, with a 4-way cache a = N c a c h a b l e i n s t r u c t i o n f e t c h e sThis figure Self-modifying code AHB behavior Instruction Memory Barrier Sample IMB sequences Noncachable instruction fetches Features S i n t e r c o n n e c t i o n S t e m b u s a r b i t e r Master will not occupy the system bus OwnershipUntil the transaction completes Locked bus sequence Relinquishing the bus Split transfers Arbiter configuration example D r e s s d e c o d i n g Address range Size System functions Master Name Hmaster30 assignment Software watchdog timerO g r a m m a b l e t i m e r s Source clock frequency Gptc characteristics Control fieldN e r a l p u r p o s e t i m e r s / c o u n t e r s Bit mode options S i c P W M f u n c t i o n Sample enhanced PWM waveform H a n c e d P W M f u n c t i o nA d r a t u r e d e code r f u n c t i o n Quadrature Encoding truth Input signalsNC No change CW Clockwise CCW Counter clockwise Err Error CCW Monitors how far the encoder has moved Typical application Testing signalsTimer support Digital filter IRQ interrupts T e r r u p t c o n t r o l l e rFIQ interrupts Vector IRQ characteristics Interrupt sources IRQ FIQ Interrupt sources are assigned as shown Interrupt ID Interrupt source N f i g u r a b l e s y s t e m a t t r i b u t e s L c o n f i g u r a t i o n O t s t r a p i n i t i a l i z a t i o n PLL configuration and control system block diagramConfiguring the powerup settings Pin name Configuration bits S t e m c o n f i g u r a t i o n r e g i s t e r s Offset 3124 2316 158 155 Isaddr System Memory Chip Select 0 Dynamic Memory Mask Address A090 N e r a l a r b i t e r C o n t r o l r e g i s t e rC 0 , B R C 1 , B R C 2 , a n d B R C 3 r e g i s t e r s Register Channel allocation Register Register bit assignment B Error D e t e c t S t a t u sChannel enable bit This is how the channels are assigned in the four registers Address A090 001C EDS1 Not reset AHB error response Not reset CPU instruction errorNot reset CPU data error Transaction type write or read M e r M a s t e r C o n t r o l r e g i s t e r AHB Error Interrupt ClearAHB Slave Error Response Detect Config EIC Timer 9 high step enable Timer 9 reload step enableTimer 9 low step enable Timer 8 reload step enable M e r 0 4 C o n t r o l r e g i s t e r s Addresses A090 0190 / 0194 / 0198 / 019C / 01A0 Debug mode Timer enableCapture and compare mode functions Timer clock select M e r 5 C o n t r o l r e g i s t e r Address A090 01A4 Reload mode TM2 M e r 6 9 C o n t r o l r e g i s t e r s Addresses A090 01A8 / 01AC / 01B0 / 01B4 D3118 Reserved D1716 M e r 6 9 H i g h r e g i s t e r s M e r 6 9 L o w r e g i s t e r s High step direction M e r 6 9 H i g h a n d L o w S t e p r e g i s t e r sM e r 6 9 R e l o a d S t e p r e g i s t e r s High step Reload step direction Reload step M e r 0 9 R e a d a n d C a p t u r e r e g i s t e r Register 3124 2316 1508 0700 Individual register mappingInterrupt Vector Address register Invert Interrupt enableA D D R r e g i s t e r Interrupt type Interrupt status active Interrupt service routine addressT e r r u p t S t a t u s a c t i v e ISA Address A090 016C T e r r u p t S t a t u s R a wF t w a r e W a t c h d o g C o n f i g u r a t i o n Israw F t w a r e W a t c h d o g T i m e r Software watchdog enableSoftware watchdog timer clock select Software watchdog interrupt clear Address A090 017C Watchdog timerO c k C o n f i g u r a t i o n r e g i s t e r CPU clock select Clock scale controlMax clock scale control Memory clock out Ethernet MAC D u l e R e s e t r e g i s t e rIO hub RST Stat Module Reset register resets each module on the AHB busReset status I2C Miscellaneous System Configuration and Status register Misaligned bus address response mode Boot modeEndian mode Internal register access mode bit PLL bypass L C o n f i g u r a t i o n r e g i s t e rPLL frequency formula Register Register bit assignment Intid W e r M a n a g e m e n tAddress A090 018C Interrupt ID Hardware clock scale control Deprecated Chip sleep enableNew designs should not use this bit Sdram self refresh control I2C wakeup CPU wake interrupt clearRTC wakeup SPI wakeup Addresses A090 01D0 / 01D4 B B u s a c t i v i t y S t a t u sAddress A090 022C Addresses A090 01D8 / 01DC Chip select 0 disableRegisters Chip select 0 base Chip select 1 base Chip select 1disableAddresses A090 01E0 / 01E4 Chip select 2 base Chip select 2 disableAddresses A090 01E8 / 01EC Chip select 3 base Chip select 3 disableAddresses A090 01F0 / 01F4 Addresses A09001F8 / 01FC Chip select 0 mask Chip select 1 disable Addresses A090 0200 Addresses A090 0208 / 020C N I D r e g i s t e r Status GenidSTS CLR RTC Module Control register controls the RTC module RTC standby mode statusC M o d u l e C o n t r o l r e g i s t e r Polarity RTC module interrupt status RTC standby modeRTC clock ready interrupt status RTC clock ready interrupt clear RTC Module Control register Static memory features, such as Memory controller provides these featuresWith and without asynchronous page mode Amba 32-bit AHB compliancy W p o w e r o p e r a t i o n Power-on reset memory map M o r y m a p Example Boot from flash Sdram remapped after boot ROM Device Write protect Mode BufferA t i c m e m o r y c o n t r o l l e r Sram Write protection Extended wait transfers Be aware Memory mapped peripherals Access sequencing and memory width Wait state generationA t i c m e m o r y i n i t i a l i z a t i o n A t i c m e m o r y r e a d c o n t r o l Programmable enableOutput enable programmable delay ROM, SRAM, and Flash Timing parameter Value External memory read transfer with zero wait statesExternal memory read transfer with two wait states WAITRD2 WAITOEN0 WAITPAGEN/A WAITWRN/A External memory read transfers with zero wait states WAITENN/A WAITTURNN/A Burst of zero wait states with fixed length Burst of two wait states with fixed length External memory page mode read transfer Y n c h r o n o u s p a g e m o d e r e a d Timing parameters Value External memory 32-bit burst read from 8-bit memoryWAITRD2 WAITOEN0 WAITPAGE1 WAITWRN/A WAITWENN/A WAITTURNN/A WAITRD0 WAITOEN0 WAITPAGE0 WAITWRN/A WAITWENN/A WAITTURNN/A Wait states added between external read and write transfers Write enable programming delayA t i c m e m o r y w r i t e c o n t r o l External memory write transfer with zero wait states External memory write transfer with two wait states WAITRDN/A WAITOENN/A WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN0 Read followed by write with no turnaround S t u r n a r o u n dS t u r n a r o u n d T i m i n g a n d p a r a m e t e r s WAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN0 Write followed by a read with no turnaround Read followed by a write with two turnaround cycles T e l a n e c o n t r o l WAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN2 D r e s s c o n n e c t i v i t y Memory banks constructed from 16-or 32-bit memory devices Memory banks constructed from 16-bit memory 2Mx32 ROM R a M I n i t i a l i z a t i o n Access sequencing and memory widthN a m i c m e m o r y c o n t r o l l e r Bit Parameter Parameter description Device size Configuration Load Mode register left shiftLeft-shift value -bit wide data bus Sdram RBC 256M 8M x 16M x 32M x 512M 64M x Device Signal Bit wide ConfigurationSignal 16M device 64M device 128M 256M 512M Left-shift value -bit wide data bus Sdram BRC BA0 BA1 Only. Bursting is not allowed G i s t e r sRegister map Address Register Description TRWL, tRDL Address A070 Reset valuesN t r o l r e g i s t e r Memory controller enable Bits Access Mnemonic DescriptionLow-power mode Address mirror Self-refresh acknowledge Srefack A t u s r e g i s t e rN f i g u r a t i o n r e g i s t e r Write buffer status N a m i c M e m o r y C o n t r o l r e g i s t e r END Sdram initialization Sync/Flash reset/power down signal dypwrnDynamic memory clock enable Self-refresh request Srefreq Refresh timer Refresh Read data strategy RAS Precharge command period tRPActive to precharge command period tRAS Self-refresh exit time tSREX Address A070 003CSrex Last-data-out to active command time tAPR APR Data-in to active command tDAL or tAPW DAL Active to active command period tRC Address A070 004C Period Auto-refresh period and auto-refresh to active commandRFC Exit self-refresh to active time command XSR Active Bank a to Active Bank B Load mode register to Active Command TimeRRD MRD Example External wait timeoutA t i c M e m o r y E x t e n d e d W a i t r e g i s t e r Address A070 0100 / 0120 / 0140 Address mapping Write protectBdmc AM1 For the Dynamic Memory ConfigurationAddress mapping 119 Description Address A070 0104 / 0124 / 0144 For a chip select connected to Select this mapping CAS latency RAS latency active to read/write delayCAS Do not modify Bsmc Buffer enablePsmc Extended wait Mode Byte lane stateChip select polarity Memory width Burst modeBmode Address A070 0208 / 0228 / 0248 Wait write enable WaitwenWait output enable Waitoen Wwen A t i c M e m o r y R e a d D e l a y 0 3 r e g i s t e r s Nonpage mode read wait states or asynchronous page modeRead first access wait state Waitrd Wtrd Asynchronous page mode read after the first wait state Wtpg Write wait states Waitwr Address A070 0218 / 0238 / 0258Wtwr Wttn Bus turnaround cycles Waitturn StaticMemory Turn Round Delay 0-3 registers Features Common acronyms Ethernet Communication Module H e r n e t M a C Ethernet communications module MAC module block diagram Features Feature Description Station address logic A t i o n a d d r e s s l o g i c S a LPHY interface mappings Media Independent Interface A t i s t i c s m o d u l e MAC receiver Receive packet processor H e r n e t f r o n t e n d m o d u l eEthernet front- end module EFE C e i v e p a c k e t p r o c e s s o r Transmit packet processor Receive buffer descriptor format description Transferring a frame to system memoryReceive buffer descriptor format A n s m i t p a c k e t p r o c e s s o r Receive buffer descriptor field definitions Definitions Transmit buffer descriptor formatTransmit buffer Descriptor field Transmitting a frame Successfully FrameTransmitted Unsuccessfully Interrupt condition Description H e r n e t s l a v e i n t e r f a c eT e r r u p t s Status bits Bit field Register Active Default Modules reset StateS e t s Multicast address Filter registers L t i c a s t a d d r e s s f i l t e r i n gFilter entries Multicast address filtering example Filtering example O c k s y n c h r o n i z a t i o nMulticast address Writing to other registers Register address Filter Eintren RxdptrEintr Txptr H e r n e t G e n e r a l C o n t r o l R e g i s t e r # Address A060 Enable TX packet processing Enable RX packet processingEnable receive DMA Accept short 64 receive frames Etxdma Enable transmit DMAEnable initialization of RX buffer descriptors Erxinit Align RX data MAC host interface soft resetRX Fifo RAM access Insert transmit source address H e r n e t G e n e r a l S t a t u s r e g i s t e r RX initialization complete H e r n e t T r a n s m i t S t a t u s r e g i s t e rRxinit Multicast frame transmitted Frame transmitted OKBroadcast frame transmitted TX abort late collision H e r n e t R e c e i v e S t a t u s r e g i s t e r Address A060 001C Receive broadcast frame Receive frame size in bytesReceive frame OK Receive multicast frame C C o n f i g u r a t i o n R e g i s t e r # Internal loopback Receive enableBits Access Mnemonic Reset Definition Excess deferral Pad/CRC enable Auto detect pad enableVlan pad enable CRC enable Frames C k t o B a c k I n t e r P a c k e t G a p r e g i s t e rPAD operation Table for transmit Type Address A060 040C Full-duplex modeHalf-duplex mode Back-to-back inter-packet-gap IPGR1 L l i s i o n W i n d o w / R e t r y r e g i s t e rAddress A060 Non back-to-back inter-packet-gap part Collision window X i m u m F r a m e r e g i s t e rCwin Retx Rmiim Reset MII management blockMaximum frame length Clock select Clocks field SettingsI M a n a g e m e n t C o m m a n d r e g i s t e r Suppress preamble If both Scan and Read are set, Scan takes precedence I M a n a g e m e n t a d d r e s s r e g i s t e rRegister bit Automatically scan for read data Address A060 042C I M a n a g e m e n t W r i t e D a t a r e g i s t e rI M a n a g e m e n t R e a d D a t a r e g i s t e r Miilf I M a n a g e m e n t I n d i c a t o r s r e g i s t e rMII read data MII link failure Nvalid A t i o n a d d r e s s r e g i s t e r sRead data not valid Automatically scan for read data in progress Station Address Register #1 A t i o n a d d r e s s F i l t e r r e g i s t e rRegister bit assignments for all three registers Station Address Register #2 PRM G i s t e r H a s h T a b l e sPRO PRA TR1K A t i s t i c s r e g i s t e r sAddress Register Transmit and receive counters Receive packet counter A060 06A0 Receive statistics Counters addressReceive byte counter A060 069C Address Register Receive counters Receive broadcast packet counter A060 06AC Receive FCS error counter A060 06A4Receive multicast packet counter A060 06A8 Rbuo Receive carrier sense error counter A060 06C8 Receive alignment error counter A060 06BCReceive code error counter A060 06C4 Receive undersize packet counter A060 06CC Transmit byte counter A060 06E0 Receive jabber counter A060 06D8Transmit statistics counters address map Address Register Transmit counters Transmit packet counter A060 06E4 Transmit excessive collision packet counter A060 These are the General Statistics registers Transmit oversize frame counter A060Transmit undersize frame counter A060 Carry Register C1RBY C1MAXC1MGV C1RPK Mask register M1RPK M1MGVM1RBY M1RFC Address A060 073C Mask register Register RXB Buffer Descriptor Pointer Address A060 0A040x00000000 RXA Buffer Descriptor Pointer RXC Buffer Descriptor Pointer Address A060 0A08Address A060 0A0C RXD Buffer Descriptor Pointer Rxovflstat H e r n e t I n t e r r u p t S t a t u s r e g i s t e rAddress A060 0A10 Rxbufc Rxdoned RxdonebRxdonec Rxnobuf H e r n e t I n t e r r u p t E n a b l e r e g i s t e r Address A060 0A14 Address A060 0A18 Address A060 0A1C Address A060 0A20 Address A060 0A24 Address A060 0A28 Address A060 0A2C Address A060 0A30 Address A060 0A34 Address A060 0A38 Rxfreed F r e e B u f f e r r e g i s t e rAddress A060 0A3C Rxfreec L t i c a s t a d d r e s s F i l t e r r e g i s t e r s Address A060 0A60 Address A060 0A58Address A060 0A5C Address A060 0A64 L t i c a s t a d d r e s s M a s k r e g i s t e r s Address A060 0A98 Address A060 0A90Address A060 0A94 Address A060 0A9C Address A060 0ABC Address A060 0AB4Address A060 0AB8 Address A060 0AC0 B u f f e r D e s c r i p t o r R a M Offset+0 Offset+C Offset+4Offset+8 Address A060 2000 512 locations M p l e h a s h t a b l e code Pointer to buffer to store hash table Pointer to hash table 337 Sample hash table code External DMA A t r a n s f e r s Source address pointer Buffer length DMA buffer descriptor diagramA b u f f e r d e s c r i p t o r Destination S c r i p t o r l i s t p r o c e s s i n g Determining the width of Pden Equation variables Use this equation to compute total access timeR i p h e r a l D M a r e a d a c c e s s Variable Definition R i p h e r a l D M a w r i t e a c c e s s Peripheral DMA single read accessPeripheral DMA burst read access REQ signal Peripheral DMA burst write accessREQ signal Logic remains paused until the REQ signal is reasserted A t i c R a M c h i p s e l e c t c o n f i g u r a t i o n Done signal Special circumstancesStatic ram chip select configuration Register name Field Value Comment A B u f f e r D e s c r i p t o r P o i n t e r A C o n t r o l r e g i s t e r Source width Channel enableChannel go Destination width Source address increment Fly-by modeDestination burst Index ResetState Buffer not ready interrupt pending Error completion interrupt pendingNormal completion interrupt pending Channel abort interrupt pending A P e r i p h e r a l C h i p S e l e c t r e g i s t e r SEL Chip select DMA Peripheral Chip Select register Is programmable for 128-, 192-, or 256-bit key lengths AESProcesses 32 bits at a time Supports ECB, CBC, OFB, CTR, and CCM cipher modes S D M a b u f f e r d e s c r i p t o r Block diagramKey size Characteristic 128 192 256 Data blocks Source buffer length AES buffer descriptor diagramSource address pointer Destination buffer length AES op code Interrupt I bit Last L bit Full F bit C r y p t i o n B p r o c e s s i n g M m o d e CCM mode does not require an initialization vectorC , C F B , O F B , a n d C T R p r o c e s s i n g Bits ContentsNonce buffer CCM mode Hub Module Interface A c o n t r o l l e rAHB slave Servicing RX and FIFOs Control13 L Source address pointer Buffer length Control15 WControl14 Control12 F Control110 Status150 Process A n s m i t D M a e x a m p l eNot applicable Pointer and Index Visual example System Memory Uart B register Address map ReservedUart a register Address map Register Offset Description Uart C register Address map Uart D register Address map Reserved SPI register Address mapAD register Address map I2C register Address map IO register Address map RTC register Address mapIO Hardware Assist register Buffer not ready interrupt pending RX Error completion interrupt pending RXNormal completion interrupt pending RX Channel abort interrupt pending RX TX Fifo service request interrupt pending RX Fifo service request interrupt pendingError completion interrupt pending TX RX Fifo overflow interrupt pending D u l e D M a R X C o n t r o l Direct Channel abortFlex I/O RX Fifo threshold RxbdpRxthrs D u l e D i r e c t M o d e R X S t a t u s F I F O D u l e D i r e c t M o d e R X D a t a F I F O Full flag D u l e D M a T X C o n t r o l Indexen Txbdp D u l e D i r e c t M o d e T X D a t a F I F O TX Fifo threshold Txdl D u l e D i r e c t M o d e T X D a t a L a s t F I F OTXD 384 Character gap timeout Modem control signal supportReceive error conditions DMA transfers to and from system memory Uart module structure Example configurationR m a l m o d e o p e r a t i o n Control register Field Value Comment This table shows the baud rates achieved with CLKref set to U d r a t e g e n e r a t o rBaud rates Divisor Baud rate R d w a r e b a s e d f l o w c o n t r o l R c e d c h a r a c t e r t r a n s m i s s i o n Force character transmission procedure Collecting feedback M w a k e u p o n c h a r a c t e r r e c o g n i t i o n DLAB=0 A p p e r C o n t r o l a n d S t a t u s r e g i s t e r sAddress Register DLAB=1 RTS A p p e r C o n f i g u r a t i o n r e g i s t e rRtsen Dtren Remote loopback SoftwareReceive character-based flow control RTS control RS485 transceiver deassertion control Enable force completeT e r r u p t E n a b l e r e g i s t e r RS485 transceiver assertion control Enable frame error Enable overflow errorEnable parity error Enable line break T e r r u p t S t a t u s r e g i s t e r Uart interrupt Parity errorFrame error Force complete Character match2 Ring indicatorCharacter match3 Character match1 Receive idle Enable receive character gap timerTransmit idle Write this field to Enable transmit bit rate generation C e i v e B u f f e r G a P C o n t r o l r e g i s t e r Data Enable character matchMask Flow control state Flow control enableFlowstate FLOW4 FLOW2 Read-only busy Force transmit enableM W a k e u p C o n t r o l r e g i s t e r Char Address 90011034 / 90019034 / 90021034 EnableA n s m i t B y t e C o u n t Txcount Rbuff R T R e c e i v e B u f f e rR T T r a n s m i t B u f f e r Tbuff R T B a u d R a t e D i v i s o r L S BR T B a u d R a t e D i v i s o r M S B Brdl Brdm Enables modem status interruptR T I n t e r r u p t E n a b l e r e g i s t e r Edssi Enables receive data available interrupt Enables receive line status interruptEnables transmit holding register empty interrupt Interrupt identification R T L i n e C o n t r o l r e g i s t e r Enable the TX and RX FifoR T F I F O C o n t r o l r e g i s t e r Clear all bytes in the TX Fifo Set break, if set TX data is set to Divisor latch access bitParity enable Stick parity, operates as follows R T L i n e S t a t u s r e g i s t e r Local loopback enable bitR T M o d e m C o n t r o l r e g i s t e r Automatic flow control R T M o d e m S t a t u s r e g i s t e r Delta DSR indicator Delta DCD indicatorTrailing edge of RI indicator Delta CTS indicator Uart Modem Status register C e i v e a n d t r a n s m i t o p e r a t i o n s Hdlc module structure Transmit operation O c k i n gT s Transmitter underflow Encoding examples T a e n c o d i n gLast byte bit Pattern table Last byte bit pattern Valid data Transitions Dpll operation Adjustment ranges and output clocks NRZ and Nrzi encoding Biphase-Level encoding CLK Address Received or a buffer close event occurs, such as end Enable valid CRC Enable Hdlc interruptEnable invalid CRC Local loopback Enable receive abort error Rabort Invalid CRC Receive abort errorHdlc interrupt Valid CRC L C D a t a R e g i s t e r Hdata Hdata Clock source L C C o n t r o l R e g i s t e rHmode L C C l o c k D i v i d e r L o w Divl L C C l o c k D i v i d e r H i g hAddress 9002911C Clock enable Divh Master mode internal diagnostic loopback Four-wire interface RXD, TXD, CLK, CSProgrammable SPI mode 0, 1, 2, or Interface SPI module I c o n t r o l l e r SPI module structure I c l o c k i n g m o d e s Timing modes Clocking mode diagramsSPI mode SPI CLK Idle Capture edge Drive edge S t e m b o o t o v e r S P I o p e r a t i o n SPI master mode SPI slave modeI c l o c k g e n e r a t i o n Clock generation samples EEPROM/FLASH header Bootmode10 Address widthAvailable Strapping options Entry Name Time to completion Entry Name Description Enable master loopback mode Configuration registers for the SPI module are located atThis is the primary SPI Configuration register I C o n t r o l a n d S t a t u s r e g i s t e r s O c k G e n e r a t i o n r e g i s t e r SPI modeSlave enable Discard bytes Register programming steps Bits Access Mnemonic Reset DivisorEnable clock generation Use this register to define the data rate of the interface D3102 Not used Write this field to D01 Parm Description Min Max Unit I t i m i n g c h a r a c t e r i s t i c sSPI master timing Parameters SPI master timing diagram SPI slave timing parameters SPI slave timing diagram SPI timing characteristics I2C bus Interface timing, data structure, and error handlingY s i c a l I 2 C b u s Overview E x t e r n a l a d d r e s s e s Slave Description Addres Bit Command Name Description C o m m a n d i n t e r f a c e Address 9005 R e g i s t e r sM m a n d T r a n s m i t D a t a r e g i s t e r RegisterDescription Provide new transmit data A t u s R e c e i v e D a t a r e g i s t e r2C Dlen port iicdlen Mcmdl S t e r a d d r e s s r e g i s t e rScmdl Irqcd A v e a d d r e s s r e g i s t e r Mask the interrupt to the ARM CPU irqdis Address 9005 000CTiming parameter for fast-mode Register Code Name Master/slave Description T e r r u p t codesMaster/slave interrupt codes F t w a r e d r i v e r I2C master software driver I2C slave high level driver O w c h a r t s Master module normal mode, 16- bit Slave module normal mode, 16- bit Real Time Clock Module C G e n e r a l C o n t r o l r e g i s t e r Address 9006 Calendar operation 12/24 clock mode operation2 4 H o u r r e g i s t e r Time date, hour, minute, second operation HRU M e r e g i s t e rHRT L e n d a r r e g i s t e r Address 9006 000C M e Alarm r e g i s t e r L e n d a r Alarm r e g i s t e r Alarm E n a b l e r e g i s t e r E n t F l a g s r e g i s t e r Address 9006 001C Date event Alarm eventMonth event Hour event Date interrupt Alarm interruptMonth interrupt Hour interrupt T e r r u p t D i s a b l e r e g i s t e r T e r r u p t E n a b l e S t a t u s r e g i s t e r N e r a l S t a t u s r e g i s t e r Address 9006 002C General Status register ADC module Structure C D M a p r o c e d u r e ADC control block C C o n f i g u r a t i o n r e g i s t e r ADC configuration registers are located at offsetC c o n t r o l a n d s t a t u s r e g i s t e r s ADC channel select DMA enableInterrupt status Wait C C l o c k C o n f i g u r a t i o n r e g i s t e rC O u t p u t R e g i s t e r s 0 Dout Absolute maximum ratings Parameter Symbola Rating UnitE c t r i c a l c h a r a c t e r i s t i c s Recommended operating conditions Parameter Symbol a Rating UnitCPU / Memory clock Power Sym Parameter Conditiona Value Unit E l e c t r i c a l c h a r a c t e r i s t i c sInputs Ouputs Sym Parameter Value Unit 74LVC1G17GW Manufacturer Part Number DescriptionNC7SP17 SN74LVC1G17DC M o r y T i m i n g Sdram burst read 16-bit Sdram burst read 16 bit, CAS latency = Sdram burst write 16 bit Sdram burst read 32 bit Sdram burst read 32 bit, CAS latency = Sdram burst write 32-bit Sdram load mode Sdram refresh mode Clock enable timing Parm Description Min Max Unit Static RAM read cycles with 0 wait states Static RAM asynchronous page mode read, Wtpg = Static RAM read cycle with configurable wait states Static RAM sequential write cycles Static RAM write cycle Static write cycle with configurable wait states Slow peripheral acknowledge timing CPU Slow peripheral acknowledge read Slow peripheral acknowledge write Ethernet timing Ethernet MII timing Standard Mode Fast Mode Parm Description Min Max Unit I2C timing SPI master parameters SPI TimingParm Description Min Max Unit Mod Not SPI slave parameters Tbclk *8 SPI master mode 0 and 1 2-byte transfer SPI master mode2 and 3 2-byte transfer SPI slave mode 0 and 1 2-byte transfer SPI slave mode 2 and 3 2-byte transfer S e t a n d h a r d w a r e s t r a p p i n g t i m i n g Parm Description Min Typ Unit A G t i m i n g System PLL reference clock Timing Diagram below pertains to clock timingO c k t i m i n g Clock timing Packaging C k a g e O c e s s o r D i m e n s i o n s C K a G I N G Processor Dimensions V i s i o n B V i s i o n C