S e t s, Status bits | Digi NS9215 guide

E T H E R N E T C O M M U N I C A T I O N M O D U L E

Resets

Interrupt condition	Description	Interrupt

No receive buffers	No buffer is available for this frame because all 4 buffer rings are	RX
	disabled, full, or no available buffer is big enough for the frame.

Receive buffers full	No buffer is available for this frame because all 4 buffers are	RX
	disabled or full.

RX buffer ready	Frame available in RX_FIFO. (Used for diagnostics.)	RX

Statistics counter	One of the statistics counters has overflowed. Individual	TX
overflow	counters can be masked using the CAM1 and CAM2 registers.

Transmit buffer closed	I bit set in Transmit buffer descriptor and buffer closed.	TX

Transmit buffer not ready	F bit not set in transmit buffer descriptor when read from TX	TX
	buffer descriptor RAM, for a frame in progress.

Transmit complete	Frame transmission complete.	TX

TXERR	Frame not transmitted successfully.	TX

TXIDLE	TX_WR logic in idle mode because there are no frames to send.	TX

Status bits	The status bits for all interrupts are available in the Ethernet Interrupt Status
	register, and the associated enables are available in the Ethernet Interrupt Enable
	register. Each interrupt status bit is cleared by writing a 1 to it.

R e s e t s

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This table provides a summary of all resets used for the Ethernet front-end and

MAC, as well as the modules the resets control.

Bit field	Register	Active	Default	Modules reset
		state	state

ERX	Ethernet General Control	0	0	RX_RD, RX_WR
	Register #1

ETX	Ethernet General Control	0	0	TX_RD, TX_WR
	Register #1

MAC_HRST	Ethernet General Control	1	0	MAC, STAT, RX_WR, TX_RD,
	Register #1			programmable registers in Station
				Address Logic

SRST	MAC1	1	1	MAC (except programmable
				registers), Station Address Logic
				(except programmable registers),
				RX_WR, TX_RD

RPERFUN	MAC1	1	0	MAC RX logic

RPEMCST	MAC1	1	0	MAC PEMCS (TX side)

274Hardware Reference NS9215

NS9215 specifications

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Digi NS9215 manual S e t s, Status bits, Bit field Register Active Default Modules reset State

Models: NS9215

Interrupt condition

Status bits

R e s e t s

Bit field

Register

Active

Default

Modules reset

state

RPEMCST

MAC1

274Hardware Reference NS9215

NS9215 specifications