S E R I A L C O N T RO L M O D U L E : S P I

SPI clock generation

S P I c l o c k g e n e r a t i o n

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Clock generation samples

The reference clock for the SPI module is the system PLL output. This clock is a nominal 300 MHz.

In SPI master mode, the clock is divided down to produce the required data rate.

In SPI slave mode, the divided down clock recovers the input SPI clock.

SPI clock generation is specified using the Clock Generation register. These are some examples of clock generation:

Interface Type

Data rate

DIVISOR

 

 

 

Master

33 Mbps

0x009

 

 

 

Master

20 Mbps

0x00F

 

 

 

Master

5 Mbps

0x03C

 

 

 

Master

500 Kbps

0x258

 

 

 

Slave

all

0x006

 

 

 

In SPI master mode

In SPI slave mode

In SPI master mode, the value programmed in the DIVISOR field must always be rounded up to the next whole integer. For example, if the required data rate is 14 Mbps, the calculation is (300 / 14) or 21.43.

The value programmed in the DIVISOR field would be 0x016. The actual data rate would be 13.64 Mbps.

The general equation is:

DIVISOR = round Up (PLL output / interface data rate)

In SPI slave mode, the value programmed in the DIVISOR field should always be 0x006. The SPI slave mode data rate is determined by the frequency of the input clock provided by the external SPI master.

S y s t e m b o o t - o v e r - S P I o p e r a t i o n

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The NET+SPI ASIC boots from an external, non-volatile, serial memory device. The device can be either a serial EEPROM or a serial Flash. In either case, the device must support a four-wire, mode0-compatible SPI interface.

The boot-over-SPI hardware interfaces to devices requiring an 8-bit address, 16-bit address, or 24-bit address. The address width is indicated by strapping pins boot_mode[1:0].

436Hardware Reference NS9215

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Digi NS9215 I c l o c k g e n e r a t i o n, S t e m b o o t o v e r S P I o p e r a t i o n, Clock generation samples

NS9215 specifications

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