Digi NS9215 manual Second-level descriptor bit assignments, Bits Large Small Tiny Description

Second-level descriptor bit assignments

WO R K I N G W I T H T H E C P U	. .
MemoryManagement Unit (MMU)..
	.
A tiny page descriptor provides the base address of a 1 KB block of memory.

Coarse page tables provide base addresses for either small or large pages. Large page descriptors must be repeated in 16 consecutive entries. Small page descriptors must be repeated in each consecutive entry.

Fine page tables provide base addresses for large, small, or tiny pages. Large page descriptors must be repeated in 64 consecutive entries. Small page descriptors must be repeated in four consecutive entries. Tiny page descriptors must be repeated in each consecutive entry.

Bits
Large	Small	Tiny	Description
[31:16]	[31:12]	[31:10]	Form the corresponding bits of the physical address.
[15:12]	---	[9:6]	SHOULD BE ZERO
[11:4]	[11:4]	[5:4]	Access permission bits. See “Domain access control” on
			page 121 and “Fault checking sequence” on page 122 for
			information about interpreting the access permission bits.
[3:2]	[3:2]	[3:2]	Indicate whether the area of memory mapped by this page
			is treated as write-back cachable, write-through cachable,
			noncached buffered, and noncached nonbuffered.
[1:0]	[1:0]	[1:0]	Indicate the page size and validity, and are interpreted as
			shown in “First-level descriptor bit assignments:
			Interpreting first level descriptor bits [1:0]” on page 111.

Second-level descriptor least significant bits

The two least significant bits of the second-level descriptor indicate the descriptor type, as shown in this table.

Value	Meaning	Description
0 0	Invalid	Generates a page translation fault.
0 1	Large page	Indicates that this is a 64 KB page.
1 0	Small page	Indicates that this is a 4 KB page.
1 1	Tiny page	Indicates that this is a 1 KB page.

Note: Tiny pages do not support subpage permissions and therefore have only one set of access permission bits.

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