Digi NS9215 manual Bits Access Mnemonic Description, Low-power mode, Address mirror

M E M O R Y C O N T RO L L E R	. .
Control register..
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Register bit

assignment	Bits	Access	Mnemonic	Description
	D31:03	N/A	Reserved	N/A (do not modify)
	D02	R/W	LPM	Low-power mode
				0 Normal mode (reset value on reset_n)
				1 Low-power mode
				Indicates normal or low-power mode. Entering low-power mode
				reduces memory controller power consumption. Dynamic memory
				is refreshed as necessary. The memory controller returns to normal
				functional mode by clearing the low-power mode bit or by power-
				on reset.
				If you modify this bit, be sure the memory controller is in idle state.
				If you modify the L bit, be aware of these conditions:
					The external memory cannot be accessed in low-power or
					disabled state. If a memory access is performed in either of these
					states, an error response is generated.
					The memory controller AHB programming port can be accessed
					normally.
					The memory controller registers can be programmed in low-
					power and/or disabled state.
	D01	R/W	ADDM	Address mirror
				0	Normal memory map
				1 Reset memory map. Static memory chip select 1 is mirrored onto
					chip select 0 and chip select 4 (reset value on reset_n)
				Indicates normal or reset memory map. On power-on reset, chip
				select 1 is mirrored to both chip select 0 and chip select 1/chip
				select 4 memory areas. Clearing the M bit allows chip select 0 and
				chip select 4 memory to be accessed.
	D00	R/W	MCEN	Memory controller enable
				0	Disabled
				1 Enabled (reset value on reset_n)

Disabling the memory controller reduces power consumption. When the memory controller is disabled, the memory is not refreshed. The memory controller is enabled by setting the enable bit or by power-on reset.

If you modify this bit, be sure the memory controller is in idle state. If you modify the E bit, be aware of these conditions:

The external memory cannot be accessed in low-power or disabled state. If a memory access is performed in either of these states, an error response is generated.

The memory controller AHB programming port can be accessed normally.

The memory controller registers can be programmed in low- power and/or disabled state.

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