Digi NS9215 manual A t i c m e m o r y i n i t i a l i z a t i o n, Memory mapped peripherals

Memory mapped peripherals

M E M O R Y C O N T RO L L E R	. .
Static memory initialization..
	.
time critical services, such as interrupt latency and low latency devices; for
example, video controllers.

Some systems use external peripherals that can be accessed using the static memory interface. Because of the way many of these peripherals function, the read and write transfers to them must not be buffered. The buffer must therefore be disabled.

S t a t i c m e m o r y i n i t i a l i z a t i o n

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Access sequencing and memory width

Wait state generation

Static memory must be initialized as required after poweron reset (reset_n) by programming the relevant registers in the memory controller as well as the configuration registers in the external static memory device.

The data width of each external memory bank must be configured by programming the appropriate bank configuration register (Static Memory Configuration 0–3). When the external memory bus is narrower that the transfer initiated from the current main bus master, the internal bus transfer takes several external bus transfers to complete.

For example, if bank 0 is configured as 8-bit wide memory and a 32-bit read is initiated, the AHB bus stalls while the memory controller reads four consecutive bytes from the memory. During these accesses, the static memory controller block demultiplexes the four bytes into one 32-bit word on the AHB bus.

Each bank of the memory controller must be configured for external transfer wait states in read and write accesses.

Configure the banks by programming the appropriate bank control registers: “StaticMemory Configuration 0–3 registers” on page 251 (StaticConfig[n])

“StaticMemory Write Enable Delay 0–3 registers” on page 254 (StaticWaitWen[n])

“Static Memory Output Enable Delay 0–3 registers” on page 255 (StaticWaitOen[n])

“Static Memory Read Delay 0–3 registers” on page 256 (StaticWaitRd[n]) “Static Memory Write Delay 0–3 registers” on page 257 (StaticWaitWr[n])

“StaticMemory Page Mode Read Delay 0–3 registers” on page 256 (StaticWaitPage[n])

“StaticMemory Turn Round Delay 0–3 registers” on page 258 (StaticWaitTurn[n])

www.digiembedded.com 209