T e l a n e c o n t r o l | Digi NS9215 instruction

M E M O R Y C O N T RO L L E R

. . .

Byte lane control. .

Timing parameters	Value

WAITRD0

WAITOEN0

WAITPAGEN/A

WAITWR0

WAITWEN0

WAITTURN2

B y t e l a n e c o n t r o l

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The memory controller generates the byte lane control signals data_mask[3:0] according to these attributes:

Little or big endian operation Transfer width

External memory bank databus width, defined within each control register The decoded address value for write accesses only

Word transfers are the largest size transfers supported by the memory controller. Any access tried with a size greater that a word causes an error response. Each memory chip select can be 8, 16, or 32 bits wide. The memory type used determines how the st_we_n and data_mask signals are connected to provide byte, halfword, and word access.

For read accesses, you must control the data_mask signals by driving them all high or all low. Do this by programming the byte lane state (PB) bit in the Static Configuration [3:0] register. See “Address connectivity” on page 222 for additional information, with respect to st_we_n and data_mask, for different memory configurations.

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Digi NS9215 manual T e l a n e c o n t r o l, WAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN2

NS9215 specifications

The Digi NS9215 is a powerful solution designed for industrial applications that require reliable connectivity and robust performance. Built on a foundation of advanced technologies, the NS9215 serves as a versatile networking device that meets the demands of automation, remote monitoring, and data acquisition.

One of the standout features of the Digi NS9215 is its multi-protocol support. It is capable of handling various communication protocols, including Ethernet, Serial, and Wireless, making it ideal for integration into heterogeneous environments. This flexibility enables users to connect legacy devices to modern networks seamlessly, facilitating smoother data communication across different platforms.

The NS9215 is equipped with powerful processing capabilities, featuring an integrated processor that ensures efficient data handling. This enables the device to perform complex data tasks without compromising performance. Its high-speed connectivity options also allow for rapid data transmission, which is crucial for real-time applications in industrial settings.

Another critical characteristic of the Digi NS9215 is its reliability in harsh environments. Built to withstand extreme temperatures, humidity, and electrical interference, this device assures consistent operation even in challenging conditions. Its rugged design minimizes the risk of failure, making it suitable for deployment in various industrial environments.

Security is a top priority for the Digi NS9215. It comes with advanced security features that protect sensitive data during transmission and prevent unauthorized access. Employing encryption protocols and secure authentication methods, the NS9215 ensures that data integrity and confidentiality are maintained throughout its operation.

The user-friendly interface of the NS9215 allows for easy configuration and management. This ease of use reduces the time required for installation and setup, enabling quick deployment in field operations. Additionally, remote management capabilities enhance operational efficiency, allowing users to monitor device performance and make adjustments from anywhere.

Furthermore, the NS9215 supports extensive scalability options. As organizations grow and evolve, the ability to scale up or adapt the networking capabilities becomes essential. With its modular design, the NS9215 can easily accommodate additional devices and protocols, ensuring longevity and continued relevance in a rapidly changing technological landscape.

In conclusion, the Digi NS9215 is a robust networking device designed for a wide range of industrial applications. Its multi-protocol support, reliability, security features, user-friendly interface, and scalability make it a valuable addition to any industrial network infrastructure, delivering performance and efficiency that businesses can depend on for critical operations.

Contents

90000847C Release date 10 April NS9215 Hardware ReferencePage Page Page Contents A p t e r 3 W o r k i n g w i t h t h e C P U 102 105 A p t e r 4 S y s t e m C o n t r o l M o d u l e 137 141 A p t e r 5 M e m o r y C o n t r o l l e r 203 Sram Bit wide configuration 228 229 Hardware Reference NS9215 HT1 315 A p t e r 7 E x t e r n a l D M a 339 Hardware Reference NS9215 A p t e r 9 I / O H u b M o d u l e 363 Hardware Reference NS9215 A p t e r 1 1 S e r i a l C o n t r o l D u l e H D L C 415 Hardware Reference NS9215 A p t e r 1 4 R e a l T i m e C l o c k M o d u l e 459 A p t e r 1 6 T i m i n g 479 A p t e r 1 7 P a c k a g i n g 513 Hardware Reference NS9215 Heading Description Pinout M o r y b u s i n t e r f a c e Pin Signal Description N O U T 2 6 H e r n e t i n t e r f a c e M a C Pin SignalSdram RAS Sdram CAS N e r a l p u r p o s e I / O G P I O CTS Uart a DCD Uart aDSR Uart a RXD Uart a CTS Uart C DCD / TXC Uart CI2C SCL Picdbgdataini CTS Uart B DCD Uart BDSR Uart B RXD Uart B RXD Uart D DSR Uart DRI Uart D TXC / DTR Uart D Pin Signal Description PIC1CLKO PIC1CLKI Pin Signal Description PIC0CLKO PIC0CLKI Pin Signal Description Pin Signal Description Pin Signal Description I/O OD S t e m c l o c k System clock drawing S t e m m o d e RTC clock and battery backup drawing Sysmode2 Sysmode1 Sysmode0 Description SPI YES S t e m r e s e t A G T e s t Adcvss POR VSS R a n d b a t t e r y b a c k e d l o g i c GND W e r a n d g r o u n d Power and ground N t r o l a n d S t a t u s r e g i s t e r s Address Description Access Reset valueSystem memory bus I/O control Register address Map Control and Status registers Bits Mnemonic Description Gpio configuration optionsI O C o n f i g u r a t i o n r e g i s t e r s Configuration Register #1 Configuration Register #0Bits Access Mnemonic Reset Description Address A0902000 Configuration Register #3 Configuration Register #2Address A0902008 Address A090200C Configuration Register #5 Configuration Register #4Address A0902010 Address A0902014 Configuration Register #7 Configuration Register #6Address A0902018 Address A090201C Configuration Register #9 Configuration Register #8Address A0902020 Address A0902024 Configuration Register #11 Configuration Register #10Address A0902028 Address A090202C Configuration Register #13 Configuration Register #12Address A0902030 Address A0902034 Configuration Register #15 Configuration Register #14Address A0902038 Address A090203C Configuration Register #17 Configuration Register #16Address A0902040 Address A0902044 Configuration Register #19 Configuration Register #18Address A0902048 Address A090204C Configuration Register #21 Configuration Register #20Address A0902050 Address A0902054 Configuration Register #23 Configuration Register #22Address A0902058 Address A090205C Configuration Register #25 Configuration Register #24Address A0902060 GPIOAddress A0902064 Address A0902068 Configuration Register #26 Address A090206C I O C o n t r o l r e g i s t e r sGpio Control Address A0902070 Address A0902074 Address A0902078 Address A0902080 I O S t a t u s r e g i s t e r sGpio Status Address A0902084 Address A090208C M o r y B u s C o n f i g u r a t i o n r e g i s t e rAddress A0902088 CS1 CS0CS2 CS3 High data bus pullup control Apudis Memory Bus Configuration register About the processor Working with the CPU S t r u c t i o n s e t s Process block DiagramArm926EJ-S ARM instruction set Thumb instruction set ARM926EJ-S system addresses Address manipulation example Accessing CP15 registersJava instruction set Mnemonics for these instructions are Terms and abbreviationsTerm Abbreviation Description For reads Register summary Be ZERO, does not cause any physical damage to the chipRegister Reads Writes TLB Writing to register R0 is Unpredictable This is the contents of the ID code registerR0 ID code Any value other than 1 or 2. Note this example Dsize and Isize fields Cache type register and field descriptionField contains these bits Field Description Size field Cache size O n t r o l r e g i s t e rAssoc field Associativity Len field Cache line length Bits Name Function Control registerBit functionality DCache behavior ICacheCache Behavior Access permissions and instructions CRm and opcode2 fields should be Zero when writing to R2R a n s l a t i o n T a b l e B a s e r e g i s t e r O m a i n a c c e s s C o n t r o l r e g i s t e r Access instructions Fault S t a t u s r e g i s t e r sE g i s t e r Register bits Priority Source Size Status Domain Fault a d d r e s s r e g i s t e rStatus and domain fields Function Description A c h e O p e r a t i o n s r e g i s t e r MVA Cache operation functionsFunction/operation Data format Instruction Modified virtual address format MVA Set/Way format Set/Way example Test and clean DCache instructions L B O p e r a t i o n s r e g i s t e r Test, clean, and invalidate DCache instructionUnpredictable Operation Data Instruction Modified virtual address format MVA A c h e L o c k d o w n r e g i s t e rCache ways That allows you to control each cache way independently Instruction or data lockdown register AccessInstructions Modifying the Cache Lockdown register Register format For each of the cache lines to be locked down in cache way 0 T L B L o c k d o w n r e g i s t e r Cache unlock procedureBit Which region the TLB entry is placed 3 P r o c e s s I D r e g i s t e r 1 a n d R 1 2 r e g i s t e r sProgramming instructions Sample code sequence Use these instructions to program the TLB Lockdown register Performing a fast context switch Fcse PID register Access instructionsRegister format This is the format of the Fcse PID register Function Data ARM instruction Accessing reading or writing this register is reserved Context ID register Access instructions4 r e g i s t e r 5 T e s t a n d d e b u g r e g i s t e r M o r y M a n a g e m e n t U n i t M M U MMU FeaturesState space servo control Protection scheme Access permissions and domains Translated entries Register Bits Description MMU program accessible registers Address translation TTB register Format Translation table base First-level fetch Table walk process Table descriptors First-level fetch concatenation and addressFirst-level descriptor Value Meaning Description Section descriptor FormatBits Section Coarse Fine Description Fine page table Section descriptor Bit descriptionDescriptor Bits Description 113 Second-level descriptor pages Second-level descriptor Second-level descriptor format Bits Large Small Tiny Description Second-level descriptor bit assignmentsSecond-level descriptor least significant bits Translation sequence for large page references Translating sequence for small page references References Translation Sequence for tinyLevel descriptor More information U Fault s a n d C P U a b o r t s Domain Fault Address register Priority encoding table Fault Address register FARFAR values for Multi-word Transfers Specifying access permissions Compatibility issuesInterpreting access permission bits M a i n a c c e s s c o n t r o l Privileged permissions User permissions Fault c h e c k i n g s e q u e n c e No access 00 Reserved Check domain status Fault checking sequence Enabling T e r n a l a b o r t sA b l i n g a n d d i s a b l i n g t h e M M U Disabling B s t r u c t u r e C h e s a n d w r i t e b u f f e r Cache features Write buffer Enabling the caches Settings Bit settingsR1 register C and M bits for DCache DCache Description ARM926EJ-S behavior Table C Table B Bit C h e M V a a n d S e t / W a y f o r m a t s Generic, virtually indexed, virtually addressed cache Cache format ARM926EJ-S This figure N c a c h a b l e i n s t r u c t i o n f e t c h e sFor example, with a 4-way cache a = Self-modifying code AHB behavior Instruction Memory Barrier Sample IMB sequences Noncachable instruction fetches S i n t e r c o n n e c t i o n Features S t e m b u s a r b i t e r Until the transaction completes OwnershipMaster will not occupy the system bus Locked bus sequence Relinquishing the bus Split transfers Arbiter configuration example Address range Size System functions D r e s s d e c o d i n g Master Name Hmaster30 assignment Software watchdog timerO g r a m m a b l e t i m e r s Source clock frequency Gptc characteristics Control fieldN e r a l p u r p o s e t i m e r s / c o u n t e r s S i c P W M f u n c t i o n Bit mode options Sample enhanced PWM waveform H a n c e d P W M f u n c t i o nA d r a t u r e d e code r f u n c t i o n NC No change CW Clockwise CCW Counter clockwise Err Error Input signalsQuadrature Encoding truth CCW Timer support Testing signalsMonitors how far the encoder has moved Typical application Digital filter FIQ interrupts T e r r u p t c o n t r o l l e rIRQ interrupts Vector IRQ FIQ IRQ characteristics Interrupt sources Interrupt ID Interrupt source Interrupt sources are assigned as shown L c o n f i g u r a t i o n N f i g u r a b l e s y s t e m a t t r i b u t e s O t s t r a p i n i t i a l i z a t i o n PLL configuration and control system block diagramConfiguring the powerup settings Pin name Configuration bits Offset 3124 2316 158 S t e m c o n f i g u r a t i o n r e g i s t e r s 155 Isaddr System Memory Chip Select 0 Dynamic Memory Mask C 0 , B R C 1 , B R C 2 , a n d B R C 3 r e g i s t e r s N e r a l a r b i t e r C o n t r o l r e g i s t e rAddress A090 Register Channel enable bit B Error D e t e c t S t a t u sChannel allocation Register Register bit assignment This is how the channels are assigned in the four registers EDS1 Address A090 001C Not reset CPU data error Not reset CPU instruction errorNot reset AHB error response Transaction type write or read AHB Slave Error Response Detect Config AHB Error Interrupt ClearM e r M a s t e r C o n t r o l r e g i s t e r EIC Timer 9 low step enable Timer 9 reload step enableTimer 9 high step enable Timer 8 reload step enable Addresses A090 0190 / 0194 / 0198 / 019C / 01A0 M e r 0 4 C o n t r o l r e g i s t e r s Capture and compare mode functions Timer enableDebug mode Timer clock select Address A090 01A4 M e r 5 C o n t r o l r e g i s t e r TM2 Reload mode Addresses A090 01A8 / 01AC / 01B0 / 01B4 M e r 6 9 C o n t r o l r e g i s t e r s D3118 Reserved D1716 M e r 6 9 H i g h r e g i s t e r s M e r 6 9 L o w r e g i s t e r s M e r 6 9 R e l o a d S t e p r e g i s t e r s M e r 6 9 H i g h a n d L o w S t e p r e g i s t e r sHigh step direction High step Reload step Reload step direction M e r 0 9 R e a d a n d C a p t u r e r e g i s t e r Register 3124 2316 1508 0700 Individual register mappingInterrupt Vector Address register A D D R r e g i s t e r Interrupt enableInvert Interrupt type T e r r u p t S t a t u s a c t i v e Interrupt service routine addressInterrupt status active ISA F t w a r e W a t c h d o g C o n f i g u r a t i o n T e r r u p t S t a t u s R a wAddress A090 016C Israw Software watchdog timer clock select Software watchdog enableF t w a r e W a t c h d o g T i m e r Software watchdog interrupt clear Address A090 017C Watchdog timerO c k C o n f i g u r a t i o n r e g i s t e r Max clock scale control Clock scale controlCPU clock select Memory clock out Ethernet MAC D u l e R e s e t r e g i s t e rIO hub Reset status Module Reset register resets each module on the AHB busRST Stat I2C Miscellaneous System Configuration and Status register Endian mode Boot modeMisaligned bus address response mode Internal register access mode bit PLL bypass L C o n f i g u r a t i o n r e g i s t e rPLL frequency formula Register Register bit assignment Address A090 018C W e r M a n a g e m e n tIntid Interrupt ID New designs should not use this bit Deprecated Chip sleep enableHardware clock scale control Sdram self refresh control RTC wakeup CPU wake interrupt clearI2C wakeup SPI wakeup Addresses A090 01D0 / 01D4 B B u s a c t i v i t y S t a t u sAddress A090 022C Registers Chip select 0 disableAddresses A090 01D8 / 01DC Chip select 0 base Chip select 1 base Chip select 1disableAddresses A090 01E0 / 01E4 Chip select 2 base Chip select 2 disableAddresses A090 01E8 / 01EC Chip select 3 base Chip select 3 disableAddresses A090 01F0 / 01F4 Chip select 0 mask Addresses A09001F8 / 01FC Addresses A090 0200 Chip select 1 disable Addresses A090 0208 / 020C N I D r e g i s t e r STS GenidStatus CLR C M o d u l e C o n t r o l r e g i s t e r RTC standby mode statusRTC Module Control register controls the RTC module Polarity RTC clock ready interrupt status RTC standby modeRTC module interrupt status RTC clock ready interrupt clear RTC Module Control register With and without asynchronous page mode Memory controller provides these featuresStatic memory features, such as Amba 32-bit AHB compliancy W p o w e r o p e r a t i o n M o r y m a p Power-on reset memory map Example Boot from flash Sdram remapped after boot A t i c m e m o r y c o n t r o l l e r Device Write protect Mode BufferROM Sram Be aware Write protection Extended wait transfers Memory mapped peripherals Access sequencing and memory width Wait state generationA t i c m e m o r y i n i t i a l i z a t i o n Output enable programmable delay Programmable enableA t i c m e m o r y r e a d c o n t r o l ROM, SRAM, and Flash External memory read transfer with two wait states External memory read transfer with zero wait statesTiming parameter Value WAITRD2 WAITOEN0 WAITPAGEN/A WAITWRN/A WAITENN/A WAITTURNN/A External memory read transfers with zero wait states Burst of two wait states with fixed length Burst of zero wait states with fixed length Y n c h r o n o u s p a g e m o d e r e a d External memory page mode read transfer WAITRD2 WAITOEN0 WAITPAGE1 WAITWRN/A WAITWENN/A WAITTURNN/A External memory 32-bit burst read from 8-bit memoryTiming parameters Value WAITRD0 WAITOEN0 WAITPAGE0 WAITWRN/A WAITWENN/A WAITTURNN/A A t i c m e m o r y w r i t e c o n t r o l Write enable programming delayWait states added between external read and write transfers External memory write transfer with zero wait states External memory write transfer with two wait states WAITRDN/A WAITOENN/A WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN0 S t u r n a r o u n d T i m i n g a n d p a r a m e t e r s S t u r n a r o u n dRead followed by write with no turnaround WAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN0 Read followed by a write with two turnaround cycles Write followed by a read with no turnaround WAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN2 T e l a n e c o n t r o l D r e s s c o n n e c t i v i t y Memory banks constructed from 16-bit memory Memory banks constructed from 16-or 32-bit memory devices 2Mx32 ROM R a M I n i t i a l i z a t i o n Access sequencing and memory widthN a m i c m e m o r y c o n t r o l l e r Bit Parameter Parameter description Device size Configuration Load Mode register left shiftLeft-shift value -bit wide data bus Sdram RBC 256M 8M x 16M x 32M x 512M 64M x Signal 16M device 64M device 128M 256M 512M Bit wide ConfigurationDevice Signal Left-shift value -bit wide data bus Sdram BRC BA1 BA0 Register map G i s t e r sOnly. Bursting is not allowed Address Register Description TRWL, tRDL Address A070 Reset valuesN t r o l r e g i s t e r Low-power mode Bits Access Mnemonic DescriptionMemory controller enable Address mirror N f i g u r a t i o n r e g i s t e r A t u s r e g i s t e rSelf-refresh acknowledge Srefack Write buffer status END N a m i c M e m o r y C o n t r o l r e g i s t e r Dynamic memory clock enable Sync/Flash reset/power down signal dypwrnSdram initialization Self-refresh request Srefreq Refresh Refresh timer Read data strategy RAS Precharge command period tRPActive to precharge command period tRAS Self-refresh exit time tSREX Address A070 003CSrex APR Last-data-out to active command time tAPR DAL Data-in to active command tDAL or tAPW Address A070 004C Active to active command period tRC Period Auto-refresh period and auto-refresh to active commandRFC XSR Exit self-refresh to active time command RRD Load mode register to Active Command TimeActive Bank a to Active Bank B MRD A t i c M e m o r y E x t e n d e d W a i t r e g i s t e r External wait timeoutExample Address A070 0100 / 0120 / 0140 Bdmc Write protectAddress mapping AM1 Address mapping Memory ConfigurationFor the Dynamic 119 Description For a chip select connected to Select this mapping Address A070 0104 / 0124 / 0144 CAS RAS latency active to read/write delayCAS latency Do not modify Psmc Buffer enableBsmc Extended wait Mode Byte lane stateChip select polarity Memory width Burst modeBmode Wait output enable Waitoen Wait write enable WaitwenAddress A070 0208 / 0228 / 0248 Wwen Read first access wait state Waitrd Nonpage mode read wait states or asynchronous page modeA t i c M e m o r y R e a d D e l a y 0 3 r e g i s t e r s Wtrd Wtpg Asynchronous page mode read after the first wait state Write wait states Waitwr Address A070 0218 / 0238 / 0258Wtwr Bus turnaround cycles Waitturn Wttn StaticMemory Turn Round Delay 0-3 registers Ethernet Communication Module Features Common acronyms Ethernet communications module H e r n e t M a C Feature Description MAC module block diagram Features PHY interface mappings A t i o n a d d r e s s l o g i c S a LStation address logic Media Independent Interface MAC receiver A t i s t i c s m o d u l e Receive packet processor H e r n e t f r o n t e n d m o d u l eEthernet front- end module EFE Transmit packet processor C e i v e p a c k e t p r o c e s s o r Receive buffer descriptor format description Transferring a frame to system memoryReceive buffer descriptor format Receive buffer descriptor field definitions A n s m i t p a c k e t p r o c e s s o r Definitions Transmit buffer descriptor formatTransmit buffer Descriptor field Transmitting a frame Transmitted FrameSuccessfully Unsuccessfully Interrupt condition Description H e r n e t s l a v e i n t e r f a c eT e r r u p t s Status bits Bit field Register Active Default Modules reset StateS e t s Filter entries L t i c a s t a d d r e s s f i l t e r i n gMulticast address Filter registers Multicast address filtering example Multicast address O c k s y n c h r o n i z a t i o nFiltering example Writing to other registers Register address Filter Eintr RxdptrEintren Txptr Address A060 H e r n e t G e n e r a l C o n t r o l R e g i s t e r # Enable receive DMA Enable RX packet processingEnable TX packet processing Accept short 64 receive frames Enable initialization of RX buffer descriptors Enable transmit DMAEtxdma Erxinit RX Fifo RAM access MAC host interface soft resetAlign RX data Insert transmit source address H e r n e t G e n e r a l S t a t u s r e g i s t e r RX initialization complete H e r n e t T r a n s m i t S t a t u s r e g i s t e rRxinit Broadcast frame transmitted Frame transmitted OKMulticast frame transmitted TX abort late collision Address A060 001C H e r n e t R e c e i v e S t a t u s r e g i s t e r Receive frame OK Receive frame size in bytesReceive broadcast frame Receive multicast frame C C o n f i g u r a t i o n R e g i s t e r # Bits Access Mnemonic Reset Definition Receive enableInternal loopback Excess deferral Vlan pad enable Auto detect pad enablePad/CRC enable CRC enable PAD operation Table for transmit C k t o B a c k I n t e r P a c k e t G a p r e g i s t e rFrames Type Half-duplex mode Full-duplex modeAddress A060 040C Back-to-back inter-packet-gap Address A060 L l i s i o n W i n d o w / R e t r y r e g i s t e rIPGR1 Non back-to-back inter-packet-gap part Cwin X i m u m F r a m e r e g i s t e rCollision window Retx Rmiim Reset MII management blockMaximum frame length I M a n a g e m e n t C o m m a n d r e g i s t e r Clocks field SettingsClock select Suppress preamble Register bit I M a n a g e m e n t a d d r e s s r e g i s t e rIf both Scan and Read are set, Scan takes precedence Automatically scan for read data Address A060 042C I M a n a g e m e n t W r i t e D a t a r e g i s t e rI M a n a g e m e n t R e a d D a t a r e g i s t e r MII read data I M a n a g e m e n t I n d i c a t o r s r e g i s t e rMiilf MII link failure Read data not valid A t i o n a d d r e s s r e g i s t e r sNvalid Automatically scan for read data in progress Register bit assignments for all three registers A t i o n a d d r e s s F i l t e r r e g i s t e rStation Address Register #1 Station Address Register #2 PRO G i s t e r H a s h T a b l e sPRM PRA TR1K A t i s t i c s r e g i s t e r sAddress Register Transmit and receive counters Receive byte counter A060 069C Receive statistics Counters addressReceive packet counter A060 06A0 Address Register Receive counters Receive multicast packet counter A060 06A8 Receive FCS error counter A060 06A4Receive broadcast packet counter A060 06AC Rbuo Receive code error counter A060 06C4 Receive alignment error counter A060 06BCReceive carrier sense error counter A060 06C8 Receive undersize packet counter A060 06CC Transmit statistics counters address map Receive jabber counter A060 06D8Transmit byte counter A060 06E0 Address Register Transmit counters Transmit packet counter A060 06E4 Transmit excessive collision packet counter A060 Transmit undersize frame counter A060 Transmit oversize frame counter A060These are the General Statistics registers Carry Register C1MGV C1MAXC1RBY C1RPK Mask register M1RBY M1MGVM1RPK M1RFC Mask register Register Address A060 073C RXB Buffer Descriptor Pointer Address A060 0A040x00000000 RXA Buffer Descriptor Pointer Address A060 0A0C Address A060 0A08RXC Buffer Descriptor Pointer RXD Buffer Descriptor Pointer Address A060 0A10 H e r n e t I n t e r r u p t S t a t u s r e g i s t e rRxovflstat Rxbufc Rxdonec RxdonebRxdoned Rxnobuf Address A060 0A14 H e r n e t I n t e r r u p t E n a b l e r e g i s t e r Address A060 0A18 Address A060 0A20 Address A060 0A1C Address A060 0A24 Address A060 0A28 Address A060 0A30 Address A060 0A2C Address A060 0A38 Address A060 0A34 Address A060 0A3C F r e e B u f f e r r e g i s t e rRxfreed Rxfreec L t i c a s t a d d r e s s F i l t e r r e g i s t e r s Address A060 0A5C Address A060 0A58Address A060 0A60 Address A060 0A64 L t i c a s t a d d r e s s M a s k r e g i s t e r s Address A060 0A94 Address A060 0A90Address A060 0A98 Address A060 0A9C Address A060 0AB8 Address A060 0AB4Address A060 0ABC Address A060 0AC0 Offset+0 B u f f e r D e s c r i p t o r R a M Offset+8 Offset+4Offset+C Address A060 2000 512 locations M p l e h a s h t a b l e code Pointer to buffer to store hash table Pointer to hash table 337 Sample hash table code A t r a n s f e r s External DMA A b u f f e r d e s c r i p t o r DMA buffer descriptor diagramSource address pointer Buffer length Destination S c r i p t o r l i s t p r o c e s s i n g R i p h e r a l D M a r e a d a c c e s s Use this equation to compute total access timeDetermining the width of Pden Equation variables Variable Definition R i p h e r a l D M a w r i t e a c c e s s Peripheral DMA single read accessPeripheral DMA burst read access REQ signal Peripheral DMA burst write accessREQ signal Logic remains paused until the REQ signal is reasserted Static ram chip select configuration Done signal Special circumstancesA t i c R a M c h i p s e l e c t c o n f i g u r a t i o n Register name Field Value Comment A B u f f e r D e s c r i p t o r P o i n t e r A C o n t r o l r e g i s t e r Channel go Channel enableSource width Destination width Source address increment Fly-by modeDestination burst Index ResetState Normal completion interrupt pending Error completion interrupt pendingBuffer not ready interrupt pending Channel abort interrupt pending A P e r i p h e r a l C h i p S e l e c t r e g i s t e r Chip select SEL DMA Peripheral Chip Select register Processes 32 bits at a time AESIs programmable for 128-, 192-, or 256-bit key lengths Supports ECB, CBC, OFB, CTR, and CCM cipher modes Key size Characteristic 128 192 256 Block diagramS D M a b u f f e r d e s c r i p t o r Data blocks Source address pointer AES buffer descriptor diagramSource buffer length Destination buffer length Interrupt I bit Last L bit Full F bit AES op code B p r o c e s s i n g C r y p t i o n M m o d e CCM mode does not require an initialization vectorC , C F B , O F B , a n d C T R p r o c e s s i n g Bits ContentsNonce buffer CCM mode Hub Module AHB slave A c o n t r o l l e rInterface Servicing RX and FIFOs Control14 Source address pointer Buffer length Control15 WControl13 L Control12 F Status150 Control110 Not applicable A n s m i t D M a e x a m p l eProcess Pointer and Index System Memory Visual example Uart a register Address map ReservedUart B register Address map Register Offset Description Uart D register Address map Uart C register Address map AD register Address map SPI register Address mapReserved I2C register Address map IO register Address map RTC register Address mapIO Hardware Assist register Normal completion interrupt pending RX Error completion interrupt pending RXBuffer not ready interrupt pending RX Channel abort interrupt pending RX Error completion interrupt pending TX RX Fifo service request interrupt pendingTX Fifo service request interrupt pending RX Fifo overflow interrupt pending D u l e D M a R X C o n t r o l Direct Channel abortFlex I/O RX Fifo threshold RxbdpRxthrs D u l e D i r e c t M o d e R X S t a t u s F I F O Full flag D u l e D i r e c t M o d e R X D a t a F I F O Indexen D u l e D M a T X C o n t r o l Txbdp TX Fifo threshold D u l e D i r e c t M o d e T X D a t a F I F O Txdl D u l e D i r e c t M o d e T X D a t a L a s t F I F OTXD 384 Receive error conditions Modem control signal supportCharacter gap timeout DMA transfers to and from system memory R m a l m o d e o p e r a t i o n Example configurationUart module structure Control register Field Value Comment Baud rates U d r a t e g e n e r a t o rThis table shows the baud rates achieved with CLKref set to Divisor Baud rate R c e d c h a r a c t e r t r a n s m i s s i o n R d w a r e b a s e d f l o w c o n t r o l M w a k e u p o n c h a r a c t e r r e c o g n i t i o n Force character transmission procedure Collecting feedback Address Register A p p e r C o n t r o l a n d S t a t u s r e g i s t e r sDLAB=0 DLAB=1 Rtsen A p p e r C o n f i g u r a t i o n r e g i s t e rRTS Dtren Receive character-based flow control SoftwareRemote loopback RTS control T e r r u p t E n a b l e r e g i s t e r Enable force completeRS485 transceiver deassertion control RS485 transceiver assertion control Enable parity error Enable overflow errorEnable frame error Enable line break T e r r u p t S t a t u s r e g i s t e r Frame error Parity errorUart interrupt Force complete Character match3 Ring indicatorCharacter match2 Character match1 Transmit idle Enable receive character gap timerReceive idle Write this field to C e i v e B u f f e r G a P C o n t r o l r e g i s t e r Enable transmit bit rate generation Data Enable character matchMask Flowstate Flow control enableFlow control state FLOW4 FLOW2 M W a k e u p C o n t r o l r e g i s t e r Force transmit enableRead-only busy Char A n s m i t B y t e C o u n t EnableAddress 90011034 / 90019034 / 90021034 Txcount Rbuff R T R e c e i v e B u f f e rR T T r a n s m i t B u f f e r R T B a u d R a t e D i v i s o r M S B R T B a u d R a t e D i v i s o r L S BTbuff Brdl R T I n t e r r u p t E n a b l e r e g i s t e r Enables modem status interruptBrdm Edssi Enables transmit holding register empty interrupt Enables receive line status interruptEnables receive data available interrupt Interrupt identification R T F I F O C o n t r o l r e g i s t e r Enable the TX and RX FifoR T L i n e C o n t r o l r e g i s t e r Clear all bytes in the TX Fifo Parity enable Divisor latch access bitSet break, if set TX data is set to Stick parity, operates as follows R T M o d e m C o n t r o l r e g i s t e r Local loopback enable bitR T L i n e S t a t u s r e g i s t e r Automatic flow control R T M o d e m S t a t u s r e g i s t e r Trailing edge of RI indicator Delta DCD indicatorDelta DSR indicator Delta CTS indicator Uart Modem Status register Hdlc module structure C e i v e a n d t r a n s m i t o p e r a t i o n s T s O c k i n gTransmit operation Transmitter underflow Last byte bit Pattern table T a e n c o d i n gEncoding examples Last byte bit pattern Valid data Transitions Dpll operation Adjustment ranges and output clocks NRZ and Nrzi encoding Biphase-Level encoding CLK Address Received or a buffer close event occurs, such as end Enable invalid CRC Enable Hdlc interruptEnable valid CRC Local loopback Rabort Enable receive abort error Hdlc interrupt Receive abort errorInvalid CRC Valid CRC Hdata L C D a t a R e g i s t e r Hdata Clock source L C C o n t r o l R e g i s t e rHmode L C C l o c k D i v i d e r L o w Divl L C C l o c k D i v i d e r H i g hAddress 9002911C Divh Clock enable Programmable SPI mode 0, 1, 2, or Four-wire interface RXD, TXD, CLK, CSMaster mode internal diagnostic loopback Interface SPI module SPI module structure I c o n t r o l l e r SPI mode SPI CLK Idle Timing modes Clocking mode diagramsI c l o c k i n g m o d e s Capture edge Drive edge I c l o c k g e n e r a t i o n SPI master mode SPI slave modeS t e m b o o t o v e r S P I o p e r a t i o n Clock generation samples Available Strapping options Bootmode10 Address widthEEPROM/FLASH header Entry Name Entry Name Description Time to completion This is the primary SPI Configuration register Configuration registers for the SPI module are located atEnable master loopback mode I C o n t r o l a n d S t a t u s r e g i s t e r s Slave enable SPI modeO c k G e n e r a t i o n r e g i s t e r Discard bytes Enable clock generation Bits Access Mnemonic Reset DivisorRegister programming steps Use this register to define the data rate of the interface D3102 Not used Write this field to D01 Parm Description Min Max Unit I t i m i n g c h a r a c t e r i s t i c sSPI master timing Parameters SPI master timing diagram SPI slave timing parameters SPI slave timing diagram SPI timing characteristics Y s i c a l I 2 C b u s Interface timing, data structure, and error handlingI2C bus Overview Slave Description Addres Bit E x t e r n a l a d d r e s s e s C o m m a n d i n t e r f a c e Command Name Description M m a n d T r a n s m i t D a t a r e g i s t e r R e g i s t e r sAddress 9005 RegisterDescription Provide new transmit data A t u s R e c e i v e D a t a r e g i s t e r2C Dlen port iicdlen Scmdl S t e r a d d r e s s r e g i s t e rMcmdl Irqcd A v e a d d r e s s r e g i s t e r Mask the interrupt to the ARM CPU irqdis Address 9005 000CTiming parameter for fast-mode Register Code Name Master/slave Description T e r r u p t codesMaster/slave interrupt codes I2C master software driver I2C slave high level driver F t w a r e d r i v e r Master module normal mode, 16- bit O w c h a r t s Slave module normal mode, 16- bit Real Time Clock Module Address 9006 C G e n e r a l C o n t r o l r e g i s t e r 2 4 H o u r r e g i s t e r 12/24 clock mode operationCalendar operation Time date, hour, minute, second operation HRU M e r e g i s t e rHRT Address 9006 000C L e n d a r r e g i s t e r M e Alarm r e g i s t e r Alarm E n a b l e r e g i s t e r L e n d a r Alarm r e g i s t e r Address 9006 001C E n t F l a g s r e g i s t e r Month event Alarm eventDate event Hour event Month interrupt Alarm interruptDate interrupt Hour interrupt T e r r u p t D i s a b l e r e g i s t e r T e r r u p t E n a b l e S t a t u s r e g i s t e r Address 9006 002C N e r a l S t a t u s r e g i s t e r General Status register Structure ADC module ADC control block C D M a p r o c e d u r e C C o n f i g u r a t i o n r e g i s t e r ADC configuration registers are located at offsetC c o n t r o l a n d s t a t u s r e g i s t e r s ADC channel select DMA enableInterrupt status Wait C C l o c k C o n f i g u r a t i o n r e g i s t e rC O u t p u t R e g i s t e r s 0 Dout Absolute maximum ratings Parameter Symbola Rating UnitE c t r i c a l c h a r a c t e r i s t i c s Recommended operating conditions Parameter Symbol a Rating UnitCPU / Memory clock Power Sym Parameter Conditiona Value Unit E l e c t r i c a l c h a r a c t e r i s t i c sInputs Sym Parameter Value Unit Ouputs NC7SP17 Manufacturer Part Number Description74LVC1G17GW SN74LVC1G17DC M o r y T i m i n g Sdram burst read 16-bit Sdram burst read 16 bit, CAS latency = Sdram burst write 16 bit Sdram burst read 32 bit Sdram burst read 32 bit, CAS latency = Sdram burst write 32-bit Sdram load mode Sdram refresh mode Clock enable timing Parm Description Min Max Unit Static RAM read cycles with 0 wait states Static RAM asynchronous page mode read, Wtpg = Static RAM read cycle with configurable wait states Static RAM sequential write cycles Static RAM write cycle Static write cycle with configurable wait states CPU Slow peripheral acknowledge timing Slow peripheral acknowledge write Slow peripheral acknowledge read Ethernet MII timing Ethernet timing I2C timing Standard Mode Fast Mode Parm Description Min Max Unit Parm Description Min Max Unit Mod Not SPI TimingSPI master parameters SPI slave parameters Tbclk *8 SPI master mode2 and 3 2-byte transfer SPI master mode 0 and 1 2-byte transfer SPI slave mode 2 and 3 2-byte transfer SPI slave mode 0 and 1 2-byte transfer Parm Description Min Typ Unit S e t a n d h a r d w a r e s t r a p p i n g t i m i n g A G t i m i n g System PLL reference clock Timing Diagram below pertains to clock timingO c k t i m i n g Clock timing C k a g e Packaging O c e s s o r D i m e n s i o n s C K a G I N G Processor Dimensions V i s i o n C V i s i o n B

Digi NS9215 T e l a n e c o n t r o l, WAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN2

Models: NS9215

Timing parameters