Digi NS9215 manual Apr, Last-data-out to active command time tAPR

M E M O R Y C O N T RO L L E R

. . .

								Dynamic Memory Data-in to Active Command Time register.
																.
Register
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								Reserved
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						Reserved									APR
Register bit
assignment	Bits		Access		Mnemonic		Description
	D31:04		N/A		Reserved		N/A (do not modify)
	D03:00		R/W		APR		Last-data-out to active command time (tAPR)

0x0–0xE

n+1 clock cycles, where the delay is in clk_out cycles.

0xF

16 clock cycles (reset value on reset_n)

D y n a m i c M e m o r y D a t a - i n t o A c t i v e C o m m a n d T i m e r e g i s t e r

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Address: A070 0040

The Dynamic Memory Data-in to Active Command Time register allows you to program the data-in to active command time, tDAL. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low- power or disabled mode. This value normally is found in SDRAM data sheets as tDAL or tAPW.

Note: The Dynamic Memory Data-in Active Command Time register is used for all four dynamic memory chip selects. The worst case value for all chip selects must be programmed.

Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							Reserved
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					Reserved									DAL

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