Digi NS9215 manual Cas, CAS latency, Do not modify, RAS latency active to read/write delay

M E M O R Y C O N T RO L L E R

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StaticMemory Configuration 0–3 registers. .

The Dynamic Memory RAS and CAS Delay 0–3 registers allow you to program the RAS and CAS latencies for the relevant dynamic memory. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low- power or disabled mode.

Note: The values programmed into these registers must be consistent with the values used to initialize the SDRAM memory device.

Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							Reserved
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		Reserved					CAS			Reserved					RAS

Register bit

assignment	Bits	Access	Mnemonic	Description
	D31:10	N/A	Reserved	N/A (do not modify)
	D09:08	R/W	CAS	CAS latency
				00	Reserved
				01	One clock cycle, where the RAS to CAS latency (RAS) and
					CAS latency (CAS) are defined in clk_out cycles
				10	Two clock cycles
				11	Three clock cycles (reset value on reset_n)
	D07:02	N/A	Reserved	N/A (do not modify)
	D01:00	R/W	RAS	RAS latency (active to read/write delay)
				00	Reserved
				01	One clock cycle, where the RAS to CAS latency (RAS) and
					CAS latency (CAS) are defined in clk_out cycles
				10	Two clock cycles
				11	Three clock cycles (reset value on reset_n)

S t a t i c M e m o r y C o n f i g u r a t i o n 0 – 3 r e g i s t e r s

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Address: A070 0200 / 0220 / 0240 / 0260

The Static Memory Configuration 0–3 registers configure the static memory configuration. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.

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