Digi NS9215 manual Reserved, Uart a register Address map, Uart B register Address map

		I / O H U B M O D U L E	. .
		Control and status register address maps..
			.
	Note: Registers 9000_0000 – 9000_7FFF and registers 9000_8000 – 9000_FFFF are
	reserved.
UART A register
address map	Register Offset	Description (31:00)
	0x9001_0000	UART A Interrupt and FIFO Status
	0x9001_0004	UART A DMA RX Control
	0x9001_0008	UART A DMA RX Buffer Descriptor Pointer
	0x9001_000C	UART A DMA RX Interrupt Configuration register
	0x9001_0010	UART A Direct Mode RX Status FIFO
	0x9001_0014	UART A Direct Mode RX Data DIDO
	0x9001_0018	UART A DMA TX Control
	0x9001_001C	UART A DMA TX Buffer Descriptor Pointer
	0x9001_0020	UART A DMA TX Interrupt Configuration register
	0x9001_0024	Reserved
	0x9001_0028	UART A Direct Mode TX Data FIFO
	0x9001_002C	UART A Direct Mode TX Data Last FIFO
	0x9001_0030 – 0x9001_0FFF	Reserved
	0x9001_1000 – 0x9001_7FFF	UART A CSR Space
UART B register
address map	Register Offset	Description (31:00)
	0x9001_8000	UART B Interrupt and FIFO Status
	0x9001_8804	UART B DMA RX Control
	0x9001_8008	UART B DMA RX Buffer Descriptor Pointer
	0x9001_800C	UART B DMA RX Interrupt Configuration register
	0x9001_8010	UART B Direct Mode RX Status FIFO
	0x9001_8014	UART B Direct Mode RX Data FIFO
	0x9001_8018	UART B DMA TX Control
	0x9001_801C	UART B DMA TX Buffer Descriptor Pointer
	0x9001_8020	UART B DMA TX Interrupt Configuration register
	0x9001_8024	Reserved
	0x9001_8028	UART B Direct Mode TX Data FIFO
	0x9001_802C	UART B Direct Mode TX Data Last FIFO

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