E T H E R N E T C O M M U N I C A T I O N M O D U L E

. .

 

 

 

 

 

 

 

 

 

 

Ethernet General Control Register #1..

 

 

 

 

 

 

.

 

 

 

 

 

 

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

Enable transmit DMA

 

D22

R/W

ETXDMA

0

 

 

 

 

 

0 Disable transmit DMA data request (use to stall

 

 

 

 

 

 

transmitter)

 

 

 

 

 

1 Enable transmit DMA data request

 

 

 

 

 

Must be set active high to allow the transmit packet

 

 

 

 

 

processor to issue transmit data requests to the AHB

 

 

 

 

 

interface.

 

 

 

 

 

Set this bit to 0 to temporarily stall frame transmission,

 

 

 

 

which always stalls at the completion of the current frame.

 

 

 

 

The 8-bit address of the next buffer descriptor to be read in

 

 

 

 

the TX buffer descriptor RAM is loaded into the TXSPTR

 

 

 

 

register when the transmit process ends.

 

 

 

 

 

If the transmit packet processor already is stalled and

 

 

 

 

 

waiting for TCLER, clearing ETXDMA will not take

 

 

 

 

 

effect until TCLER has been toggled.

 

 

 

 

 

This bit generally should be set after the Ethernet transmit

 

 

 

 

parameters (for example, buffer pointer descriptor) are

 

 

 

 

programmed into the transmit packet processor.

 

 

 

 

 

 

 

D21

R/W

Not used

1

Always write as 1.

 

 

 

 

 

 

 

D20

R/W

Not used

0

Always write as 0.

 

 

 

 

 

 

 

D19

R/W

ERXINIT

0

Enable initialization of RX buffer descriptors

 

 

 

 

 

0

Do not initialize

 

 

 

 

 

1

Initialize

 

 

 

 

 

When set, causes the RX_RD logic to initialize the internal

 

 

 

 

buffer descriptor registers for each of the four pools from

 

 

 

 

the buffer descriptors pointed to by RXAPTR, RXBPTR,

 

 

 

 

RXCPTR, and RXDPTR. This is done as part of the RX

 

 

 

 

initialization process. RXINIT is set in the Ethernet

 

 

 

 

 

General Status register when the initialization process is

 

 

 

 

complete, and ERXINIT must be cleared before enabling

 

 

 

 

frame reception from the MAC.

 

 

 

 

 

The delay from ERXINIT set to RXINIT set is less than

 

 

 

 

five microseconds.

 

 

 

 

 

 

 

 

D18:13

N/A

Reserved

N/A

N/A

 

 

 

 

 

 

 

 

D12

R/W

Not used

0

Always write as 0.

 

 

 

 

 

 

 

D11

R/W

RXSHFT

0

Shift RX data

 

 

 

 

 

0 Standard receive format. No padding bytes added

 

 

 

 

 

 

before receive frame data

 

1 The receiver inserts 2 bytes of padding before the first byte of the receive data, to create longword alignment of the payload.

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Digi NS9215 manual Enable transmit DMA, Etxdma, Erxinit, Enable initialization of RX buffer descriptors, Rxshft

NS9215 specifications

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