S Y S T E M C O N T RO L M O D U L E

System bus arbiter

S y s t e m b u s a r b i t e r

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High speed bus system

High-speed bus arbiters

How the bus arbiter works

The bus arbitration mechanism ensures that only one bus master has access to the system bus at any time. If you are using a system in which bus bandwidth allocation is critical, you must be sure that your worst-case bus bandwidth allocation goals can be met. See “Arbiter configuration example” on page 140 for information about configuring the AHB arbiter.

The high-speed bus system is split into two subsystems:

High-speed peripheral subsystem: Connects all high-speed peripheral devices to a port on the external memory controller.

CPU subsystem: Connects the CPU directly to a second port on the external memory controller.

The high-speed bus contains two arbiters: one for the ARM926 (CPU) and one for the main bus.

CPU arbiter. Splits the bandwidth 50–50 between the data and instruction interfaces. If the CPU access is to external memory, no further arbitration is necessary; the CPU has immediate access to external memory through slave port 0 on the memory controller. If CPU access is to one of the peripherals on the main bus, however, the main arbiter will arbitrate the access.

Main arbiter. Contains a 16-entry Bus Request Configuration (BRC) register. Each BRC entry represents a bus request and grant channel. Each request/grant channel can be assigned to only one bus master at a time. Each bus master can be connected to multiple request/grant channels simultaneously, however, depending on the bus bandwidth requirement of that master.

Each request/grant channel has a two-bit Bandwidth Reduction Field (BRF) to determine how often each channel can arbitrate for the system bus — 100%, 75%, 50%, or 25%. A BRF value of 25%, for example, causes a channel to be skipped every 3 or 4 cycles. The BRC gates the bus requesting signals going into a 16-entry Bus Request register (BRR). As a default, unassigned channels in the BRC block the corresponding BRR entries from being set by any bus request signals. On powerup, only the CPU is assigned to one of the channels with 100% bandwidth strength as the default setting.

1The arbiter evaluates the BRR at every bus clock until one or more bus requests are registered.

138Hardware Reference NS9215

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Digi NS9215 manual S t e m b u s a r b i t e r

NS9215 specifications

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