WO R K I N G W I T H T H E C P U

R4 register

R 4 r e g i s t e r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Accessing (reading or writing) this register causes UNPREDICTABLE behavior.

R 5 : F a u l t S t a t u s r e g i s t e r s

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Register R5 accesses the Fault Status registers (FSRs). The Fault Status registers contain the source of the last instruction or data fault. The instruction-side FSR is intended for debug purposes only.

The FSR is updated for alignment faults and for external aborts that occur while the MMU is disabled. The FSR accessed is determined by the opcode_2 value:

opcode_2=0

Data Fault Status register (DFSR)

opcode_2=1

Instruction Fault Status register (IFSR)

Access instructions

See "MemoryManagement Unit (MMU)," beginning on page 105, for the fault type encoding.

Access the FSRs using these instructions:

MRC p15, 0, Rd, c5, c0, 0; read DFSR

MCR p15, 0, Rd, c5, c0, 0; write DFSR

MRC p15, 0, Rd, c5, c0, 1; read IFSR

MCR p15, 0, Rd, c5, c0, 1; write IFSR

Register format

31

9

8

7

4

3

0

UNP/SBZ

0

Domain

Status

Register bits

BitsDescription

[31:9]

UNPREDICTABLE/SHOULD BE ZERO

[8]Always reads as zero. Writes are ignored.

[7:4]

Specifies which of the 16 domains (D15–D0) was being accessed when a data fault

 

occurred.

 

 

[3:0]

Type of fault generated. (See "MemoryManagement Unit (MMU)," beginning on page

 

105.)

 

 

92Hardware Reference NS9215

Page 92
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Digi NS9215 manual E g i s t e r, Fault S t a t u s r e g i s t e r s, Access instructions, Register bits, BitsDescription

NS9215 specifications

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