T I M I N G

Reset and edge sensitive input timing requirements

Ouputs

All electrical outputs are 3.3V interface.

 

 

 

 

DC electrical outputs are provided below.

 

 

 

 

 

 

 

 

 

 

Sym

Parameter

Value

 

Unit

 

 

 

 

 

 

 

VOH

High-level output voltage (LVTTL level)

Min

VDDA-0.6

V

 

VIL

Low-level input voltage:

Max

0.4

V

 

 

LVTTL level

 

 

 

 

 

 

 

 

 

R e s e t a n d e d g e s e n s i t i v e i n p u t t i m i n g r e q u i r e m e n t s

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The critical timing requirement is the rise and fall time of the input. If the rise time is too slow for the reset input, the hardware strapping options may be registered incorrectly. If the rise time of a positive-edge-triggered external interrupt is too slow, then an interrupt may be detected on both the rising and falling edge of the input signal.

A maximum rise and fall time must be met to ensure that reset and edge sensitive inputs are handled correctly. With Digi processors, the maximum is 500 nanoseconds as shown:

 

tR

reset_n or positive edge input

tR

max = 500nsec

VIN

= 0.8V to 2.0V

 

tF

negative edge input

tF

max = 500nsec

VIN

= 2.0V to 0.8V

482Hardware Reference NS9215

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Digi NS9215 manual Ouputs, Sym Parameter Value Unit

NS9215 specifications

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