S E R I A L C O N T RO L M O D U L E : S P I

. . .

System boot-over-SPI operation. .

Available

strapping options

boot_mode[1:0]

Address width

 

 

 

 

00

Disabled

 

 

 

 

01

8-bit address

 

 

 

 

10

16-bit address

 

 

 

 

11

24-bit address

 

 

 

EEPROM/FLASH header

The boot-over-SPI hardware requires several pieces of user-supplied information to complete the boot operation. This information must be located in a 128-byte header starting at address zero in the external memory device. Each entry in the header is four bytes long.

Header format This is the format of the 128-byte header.

Entry

Name

0x0

Size[19:0]

 

(31:20 reserved)

Description

Total number of words to fetch from the SPI-EEPROM. The total must include the 32-word header:

(Code image size in bytes + 128) / 4)

0x4

Mode[27:0]

 

(31:28 reserved)

All SDRAM components contain a Mode register. This register contains control information required to successfully access the component. The fields (available in any SDRAM specification) are defined as follows:

Burst length: 4 for 32-bit data bus, 8 for 16-bit data bus

Burst type: Sequential

CAS latency: Component-specific; 2 or 3

OpMode: Standard

Write burst mode: Programmed burst length

This value must be left-shifted such that it is aligned to the row address bits as specified in “Address mapping,” beginning on page 229. For example, 4Mx16 components can be combined to create a 32-bit bus. These parts require 12 row address bits. With a CAS2 access, the Mode register contents would be 0x22. This value is shifted 12 places to the left (0x00022000) to form the value in the SDRAM config field.

0x8

Divisor[9:0]

 

(31:10 reserved)

Defines the interface data rate for the boot-over-SPI operation after the initial 16-bytes. A data rate of about 375 Kbps fetches the 16-byte header. See the Clock Generation register for more details.

0xc

HS Read[0]

A 1 indicates the external device supports high-speed read

 

(31:1 reserved)

operation. Serial FLASH devices operating above 20MHz

 

 

generally support this feature.

 

 

 

0x10

Config register

See the Memory Controller chapter.

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Digi NS9215 manual Available Strapping options, EEPROM/FLASH header, Bootmode10 Address width, Entry Name

NS9215 specifications

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