Digi NS9215 manual T e r r u p t c o n t r o l l e r, FIQ interrupts, IRQ interrupts, Vector

S Y S T E M C O N T RO L M O D U L E

Interrupt controller

I n t e r r u p t c o n t r o l l e r

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The interrupt system is a simple two-tier priority scheme. Two lines access the CPU core and can interrupt the processor: IRQ (normal interrupt) and FIQ (fast interrupt). FIQ has a higher priority than IRQ.

FIQ interrupts	Most sources of interrupts on the processor are from the IRQ line. There is only one
	FIQ source for timing-critical applications. The FIQ interrupt generally is reserved
	for timing-critical applications for these reasons:
	The interrupt service routine is executed directly without determining the
	source of the interrupt.
	Interrupt latency is reduced. The banked registers available for FIQ interrupts
	are more efficient because a context save is not required.
	Note: The interrupt source assigned to the FIQ must be assigned to the highest
	priority, which is 0.
IRQ interrupts	IRQ interrupts come from several different sources in the processor and are
	managed using the Interrupt Config registers (see “Int (Interrupt) Config
	(Configuration) 31–0 registers” on page 175). IRQ interrupts can be enabled or
	disabled on a per-level basis using the Interrupt Enable registers. These registers
	serve as masks for the different interrupt levels. Each interrupt level has two
	registers:
	Interrupt Configuration register. Use this register to assign the source for
	each interrupt level, invert the source polarity, select IRQ or FIQ, and enable
	the level.
	Interrupt Vector Address register. Contains the address of the interrupt
	service routine.
32-vector	The next figure shows a 32-vector interrupt controller:
interrupt
controller

148Hardware Reference NS9215