Digi NS9215 manual Tbclk *8

T I M I N G

Memory Timing

Parm	Description	Min	Max	Unit	Mod	Not
					es	es
SP22	SPI enable low hold from last SPI CLK in	15		ns	0,3	1
	falling
SP23	SPI enable low hold from last SPI CLK in	15		ns	1,2	1
	rising
SP24	SPI CLK in high time	SP26*40%	SP26*60%	ns	0,1,2,	5
					3
SP25	SPI CLK in low time	SP26*40%	SP26*60%	ns	0,1,2,	5
					3
SP26	SPI CLK in period	TBCLK*8		ns	0,1,2,
					3

Notes:

1Active level of SPI enable is inverted (that is, 1) if the CSPOL bit in Serial Channel Control Register B is set to a 1. Note that in SPI slave mode, only a value of 0 (low enable) is valid; the SPI slave is fixed to an active low chip select.

2SPI data order is reversed (that is, LSB last and MSB first) if the BITORDR bit in Serial Channel Control Register B is set to a 0.

3TBCLK is period of AHB clock.

4± 5% duty cycle skew.

5± 10% duty cycle skew.

6Cload = 5pf for all outputs.

7SPI data order can be reversed such that LSB is first. Use the BITORDR bit in Serial Channel B/A/C/D Control Register A.

506Hardware Reference NS9215