Digi NS9215 manual Read data strategy

M E M O R Y C O N T RO L L E R

Dynamic Memory Precharge Command Period register

Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							Reserved
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Reserved

RD

Register bit

assignment	Bits	Access	Mnemonic	Description
	D31:02	N/A	Reserved	N/A (do not modify)
	D01:00	R/W	RD	Read data strategy
				00	Reserved.
				01	Command delayed strategy, using CLKDELAY (command
					delayed, clock out not delayed).
				10	Command delayed strategy plus one clock cycle, using
					CLKDELAY (command delayed, clock out not delayed).
				11	Command delayed strategy plus two clock cycles, using
					CLKDELAY (command delayed, clock out not delayed).

D y n a m i c M e m o r y P r e c h a r g e C o m m a n d P e r i o d r e g i s t e r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address: A070 0030

The Dynamic Memory Precharge Command Period register allows you to program the precharge command period, tRP. Modify this register only during system initialization. This value normally is found in SDRAM datasheets as tRP.

Note: The Dynamic Memory Precharge Command Period register is used for all four dynamic memory chip selects. The worst case value for all chip selects must be programmed.

Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							Reserved
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					Reserved									RP

238Hardware Reference NS9215