Transmit packet processor

E T H E R N E T C O M M U N I C A T I O N M O D U L E

. .

 

Receive packet processor..

 

.

The 2K byte RX_FIFO allows the entire Ethernet frame to be buffered while the receive byte count is analyzed. The receive byte count is analyzed by the receive packet processor to select the optimum-sized buffer for transferring the received frame to system memory. The processor can use one of four different-sized receive buffers in system memory.

The transmit packet processor transfers frames constructed in system memory to the Ethernet MAC. The software initializes a buffer descriptor table in a local RAM that points the transmit packet processor to the various frame segments in system memory. The 256-byte TX_FIFO decouples the data transfer to the Ethernet MAC from the AHB bus fill rate.

R e c e i v e p a c k e t p r o c e s s o r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

As a frame is received from the Ethernet MAC, it is stored in the receive data FIFO. At the end of the frame, an accept/reject decision is made based on several conditions. If the packet is rejected, it is flushed from the receive data FIFO.

If a frame is accepted, status signals from the MAC, including the receive size of the frame, are stored in a separate 32-entry receive status FIFO; the RX_RD logic is notified that a good frame is in the FIFO.

If the RX_WR logic tries to write to a full receive data FIFO anytime during the frame, it flushes the frame from the receive data FIFO and sets RXOVFL_DATA (RX data FIFO overflowed) in the Ethernet Interrupt Status register. For proper operation, reset the receive packet processor using the ERX bit in the Ethernet General Control Register #1 when this condition occurs. If the RX_WR logic tries to write a full receive status FIFO at the end of the frame, the RX_WR logic flushes the frame from the receive data FIFO and sets RXOVFL_STAT (RX status FIFO overflowed) in the Ethernet Interrupt Status register.

Power down mode The RX_WR logic supports the processor system power down and recovery functionality. In this mode, the RX clock to the MAC and the RX_WR logic are still active, but the clock to the RX_RD and AHB interface is disabled. This allows frames to be received and written into the receive FIFO, but the frame remains in the FIFO until the system wakes up. Normal frame filtering is still performed.

When a qualified frame is inserted into the receive FIFO, the receive packet processor notifies the system power controller, which performs the wake up sequence. The frame remains in the receive FIFO until the system wakes up.

www.digiembedded.com

267

Page 267
Image 267
Digi NS9215 manual C e i v e p a c k e t p r o c e s s o r, Transmit packet processor

NS9215 specifications

The Digi NS9215 is a powerful solution designed for industrial applications that require reliable connectivity and robust performance. Built on a foundation of advanced technologies, the NS9215 serves as a versatile networking device that meets the demands of automation, remote monitoring, and data acquisition.

One of the standout features of the Digi NS9215 is its multi-protocol support. It is capable of handling various communication protocols, including Ethernet, Serial, and Wireless, making it ideal for integration into heterogeneous environments. This flexibility enables users to connect legacy devices to modern networks seamlessly, facilitating smoother data communication across different platforms.

The NS9215 is equipped with powerful processing capabilities, featuring an integrated processor that ensures efficient data handling. This enables the device to perform complex data tasks without compromising performance. Its high-speed connectivity options also allow for rapid data transmission, which is crucial for real-time applications in industrial settings.

Another critical characteristic of the Digi NS9215 is its reliability in harsh environments. Built to withstand extreme temperatures, humidity, and electrical interference, this device assures consistent operation even in challenging conditions. Its rugged design minimizes the risk of failure, making it suitable for deployment in various industrial environments.

Security is a top priority for the Digi NS9215. It comes with advanced security features that protect sensitive data during transmission and prevent unauthorized access. Employing encryption protocols and secure authentication methods, the NS9215 ensures that data integrity and confidentiality are maintained throughout its operation.

The user-friendly interface of the NS9215 allows for easy configuration and management. This ease of use reduces the time required for installation and setup, enabling quick deployment in field operations. Additionally, remote management capabilities enhance operational efficiency, allowing users to monitor device performance and make adjustments from anywhere.

Furthermore, the NS9215 supports extensive scalability options. As organizations grow and evolve, the ability to scale up or adapt the networking capabilities becomes essential. With its modular design, the NS9215 can easily accommodate additional devices and protocols, ensuring longevity and continued relevance in a rapidly changing technological landscape.

In conclusion, the Digi NS9215 is a robust networking device designed for a wide range of industrial applications. Its multi-protocol support, reliability, security features, user-friendly interface, and scalability make it a valuable addition to any industrial network infrastructure, delivering performance and efficiency that businesses can depend on for critical operations.