Cache unlock procedure

WO R K I N G W I T H T H E C P U

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R10:TLB Lockdown register..

 

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8Write <CRm>==0 to Cache Lockdown register (R9), setting L==1 for bit i and restoring all other bits to the values they had before the lockdown routine was started.

To unlock the locked down portion of the cache, write to Cache Lockdown register (R9) setting L==0 for the appropriate bit. The following sequence, for example, sets the L bit to 0 for way 0 of the ICache, unlocking way 0:

MRC p15, 0, Rn, c9, c0, 1;

BIC Rn, Rn, 0x01;

MCR p15, 0, Rn, c9, c0, 1;

R 1 0 : T L B L o c k d o w n r e g i s t e r

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The TLB Lockdown register controls where hardware page table walks place the TLB entry — in the set associative region or the lockdown region of the TLB. If the TLB entry is put in the lockdown region, the register indicates which entry is written. The TLB lockdown region contains eight entries (see the discussion of the TLB structure in "TLB structure," beginning on page 126, for more information).

Register format

31

29

28

26

25

SBZ

 

Victim

 

SBZ/UNP

 

 

 

 

 

0

P

P bit

When writing the TLB Lockdown register, the value in the P bit (D0) determines in

 

which region the TLB entry is placed:

 

P=0

Subsequent hardware page table walks place the TLNB entry in the set associative region

 

 

of the TLB.

 

P=1

Subsequent hardware page table walks place the TLB entry in the lockdown region at the

 

 

entry specified by the victim, in the range 0–7.

Invalidate operation

TLB entries in the lockdown region are preserved so invalidate-TLB operations only invalidate the unpreserved entries in the TLB; that is, those entries in the set- associative region. Invalidate-TLB single entry operations invalidate any TLB entry corresponding to the modified virtual address given in Rd, regardless of the entry’s preserved state; that is, whether they are in lockdown or set-associative TLB regions. See “R8:TLB Operations register” on page 97 for a description of the TLB- invalidate operations.

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Digi NS9215 manual T L B L o c k d o w n r e g i s t e r, Cache unlock procedure, Bit, Which region the TLB entry is placed

NS9215 specifications

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