I / O H U B M O D U L E

. . .

[Module] RX Interrupt Configuration register. .

Register

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RXBDP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RXBDP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register bit

assignment

Bit(s)

Access

Mnemonic

Reset

Description

 

 

 

 

 

 

 

D31:00

R/W

RXBDP

0x0

The first buffer descriptor in the ring. Used when

 

 

 

 

 

the W bit is found, which indicates the last buffer

 

 

 

 

 

descriptor in the list.

 

 

 

 

 

 

[ M o d u l e ] R X I n t e r r u p t C o n f i g u r a t i o n r e g i s t e r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Addresses: 9000_000C / 9000_800C / 9001_000C / 9001_800C / 9002_000C / 9002_800C / 9003_000C / 9000_800C

The RX Interrupt Configuration register allows system software to configure the interrupt for the I/O hub module receive channel.

Register

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RXTHRS

Reser ved

RXFOFIE RXFSRIE RXNCIE RXECIE RXNRIE RXCAIE RXPCIE WSTAT ISTAT

LSTAT

FSTAT

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

BLENSTAT

Register bit

assignment

Bit(s)

Access

Mnemonic

Reset

Description

 

 

 

 

 

 

 

D31:28

R/W

RXTHRS

0xF

RX FIFO threshold

 

 

 

 

 

An interrupt is generated when the FIFO level

 

 

 

 

 

rises above this level.

 

 

 

 

 

 

 

D27

N/A

Reserved

N/A

N/A

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Image 377
Digi NS9215 manual Rxbdp, Rxthrs, RX Fifo threshold

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