I / O H U B M O D U L E

DMA controller

 

 

For transmit channels. CPU sets the F bit after the data is written to a buffer.

 

 

The DMA controller clears this bit as each buffer is read from external memory.

 

 

If the DMA controller ever finds that this bit is not set when the buffer

 

 

descriptor is read, the NRIP bit is set in the Interrupt Status register and the

 

 

DMA controller stops immediately and goes to the ERROR state. The CPU must

 

 

clear the CE bit to restore the DMA.

 

 

For receive channels, hardware sets the F bit after data is written to a buffer.

 

 

The CPU must clear the F bit after all data has been read from the buffer. If

 

 

the DMA controller ever finds that this bit is not clear when the buffer

 

 

descriptor is read, the NRIP bit is set in the Interrupt Status register and the

 

 

DMA controller stops immediately.

 

 

The DMA controller must be soft reset after the buffer descriptor problem

 

 

has been solved.

Control[11:0]

These bits are not used.

Status[15:0]

The status depends on the module, as defined in the next tables.

 

Note: In direct mode, the status can be read from the Direct Mode RX Status FIFO.

 

UART

 

 

 

 

Bits

Description

 

 

 

 

15:7

Reserved

 

 

 

 

6:5

01 Error; bits 3:0 indicate the error type

 

 

bit 4: Reserved

 

 

bit 3: Receiver overflow, should never occur in a properly configured system

bit 2: Parity error

bit 1: Framing error

bit 0: Break condition

366

Hardware Reference NS9215

31 March 2008

Page 366
Image 366
Digi NS9215 manual Control110, Status150

NS9215 specifications

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