Digi NS9215 manual External memory read transfers with zero wait states, Waitenn/A Waitturnn/A

M E M O R Y C O N T RO L L E R

Static memory read: Timing and parameters

External memory read transfer with two output enable delay states

Timing parameter Value

WAITENN/A

WAITTURNN/A

This diagram shows an external memory read transfer with two output enable delay states (WAITOEN=2). Seven AHB cycles are required for the transfer, five for the standard read and an additional two because of the output delay states added.

clk_out

addr A

data D(A)

cs[n]

st_oe_n

Timing parameter Value

WAITRD2

WAITOEN2

WAITPAGEN/A

WAITWRN/A

WAITWENN/A

WAITTURNN/A

External memory read transfers with zero wait states

This diagram shows external memory read transfers with zero wait states

(WAITRD=0). These transfers can be non-sequential transfers or sequential transfers of a specified burst length. Bursts of unspecified length are interpreted as INCR4 transfers. All transfers are treated as separate reads, so have the minimum of five AHB cycles added.

clk_out

addr A 0 B

data D(A) D(B)

cs[n] st_oe_n

212Hardware Reference NS9215