Transmit oversize frame counter (A060 0724)

E T H E R N E T C O M M U N I C A T I O N M O D U L E

Statistics registers

Incremented for each transmitted frame that exceeds 1518 bytes (NON_VLAN) or 1532 bytes (VLAN) and contains a valid FCS.

D31:12

R

Reset = Read as 0

Reserved

D11:00

R/W

Reset = 0x000

TOVR

Transmit undersize frame counter (A060 0728)

Incremented for every frame less than 64 bytes, with a correct FCS value. This counter also is incremented when a jumbo packet is aborted and the MAC is not checking the FCS, because the frame is reported as having a length of 0 bytes.

D31:12

R

Reset = Read as 0

Reserved

D11:00

R/W

Reset = 0x000

TUND

Transmit fragment counter (A060 072C)

General Statistics registers address map

Incremented for every frame less than 64 bytes, with an incorrect FCS value.

D31:12

R

Reset = Read as 0

Reserved

D11:00

R/W

Reset = 0x000

TFRG

These are the General Statistics registers.

Address

Register

General registers

R/W

 

 

 

 

A060_0730

CAR1

Carry Register 1

R

 

 

 

 

A060_0734

CAR2

Carry Register 2

R

 

 

 

 

A060_0738

CAM1

Carry Register 1 Mask register

R/W

 

 

 

 

A060_073C

CAM2

Carry Register 2 Mask register

R/W

 

 

 

 

Carry Register 1 (CAR1) and Carry Register 2 (CAR2) have carry bits for all of the statistics counters. These carry bits are set when the associated counter reaches a rollover condition.

These carry bits also can cause the STOVFL (statistics counter overflow) bit in the Ethernet Interrupt Status register to be set. Carry Register 1 Mask register (CAM1) and Carry Register 2 Mask register (CAM2) have individual mask bits for each of the carry bits. When set, the mask bit prevents the associated carry bit from setting the STOVFL bit.

Carry Register 1

Address: A060 0730

310Hardware Reference NS9215

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Digi NS9215 manual Transmit oversize frame counter A060, Transmit undersize frame counter A060, Carry Register

NS9215 specifications

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