WO R K I N G W I T H T H E C P U

. .

 

Caches and write buffer..

 

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ICache I and M This table gives the I and M bit settings for the ICache, and the associated behavior. bit settings

R1 I bit

R1 M bit

ARM926EJ-S behavior

 

 

 

0

-----

ICache disabled. All instruction fetches are fetched from external memory

 

 

(AHB).

 

 

 

1

0

ICache enabled, MMU disabled. All instruction fetches are cachable, with no

 

 

protection checks. All addresses are flat-mapped; that is, VA=MVA=PA.

 

 

 

1

1

ICache enabled, MMU enabled. Instruction fetches are cachable or

 

 

noncachable, depending on the page descriptor C bit (see “ICache page table

 

 

C bit settings” on page 129), and protection checks are performed. All

 

 

addresses are remapped from VA to PA, depending on the page entry; that

 

 

is, the VA is translated to MVA and the MVA is remapped to a PA.

 

 

 

ICache page table This table shows the page table C bit settings for the ICache (R1 I bit = M bit = 1).

C bit settings

Page table C

Description

ARM926EJ-S behavior

bit

 

 

 

 

 

 

0

Noncachable

ICache disabled. All instruction fetches are fetched from external

 

 

memory.

 

 

 

 

 

1

Cachable

Cache hit

Read from the ICache.

 

 

Cache miss Linefill from external memory.

 

 

 

 

R1 register C and M bits for DCache

This table gives the R1: Control register C and M bit settings for DCache, and the associated behavior.

R1 C bit

R1 M bit

ARM926EJ-S behavior

 

 

 

0

0

DCache disabled. All data accesses are to the external memory.

 

 

 

1

0

DCache enabled, MMU disabled. All data accesses are noncachable,

 

 

nonbufferable, with no protection checks. All addresses are flat-mapped; that

 

 

is, VA=MVA=PA.

 

 

 

1

1

DCache enabled, MMU enabled. All data accesses are cachable or

 

 

noncachable, depending on the page descriptor C bit and B bit (see “DCache

 

 

page table C and B settings” on page 129), and protection checks are

 

 

performed. All addresses are remapped from VA to PA, depending on the

 

 

MMU page table entry; that is, the VA is translated to an MVA and the MVA

 

 

is remapped to a PA.

 

 

 

DCache page

This table gives the page table C and B bit settings for the DCache (R1: Control

table C and B

register C bit = M bit = 1), and the associated behavior.

settings

 

www.digiembedded.com

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Page 129
Image 129
Digi NS9215 manual Bit settings, R1 register C and M bits for DCache, Table C and B, Settings

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