I 2 C M A S T E R / S L A V E I N T E R F A C E

. .

 

 

 

 

 

 

 

 

 

Interrupt Codes..

 

 

 

 

 

.

 

 

 

 

 

 

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

 

 

D12:09

R/W

SFW

0xF

Spike filter width

 

 

 

 

 

A default value of 1 is recommended. Available

 

 

 

 

values are 0–15.

 

 

 

 

 

 

 

D08:00

R/W

CLREF

0x0

clk_ref[9:1]

 

 

 

 

 

The I2C clock on port iic_scl_out is generated

 

 

 

 

by the system clock divided by the 10-bit value

 

 

 

 

of clk_ref.

 

The LSB of clk_ref cannot be programmed, and is set to 0 internally. The programmed value of clk_ref[9:1] must be greater than 3.

I n t e r r u p t C o d e s

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupts are signaled in the irq_code field in the STATUS_REG, by providing the appropriate interrupt code (see “Master/slave interrupt codes” on page 455). The ARM CPU waits for an interrupt by polling the STATUS_REG or checking the irq signal. An interrupt is cleared by reading the STATUS_REG, which also forces the irq signal down (minimum one cycle if another interrupt is stored).

Note: RX_DATA_REG contains only a received byte if it is accessed after a RX_DATA master or slave interrupt is signaled. At all other times, the internal master or slave shift register is accessed with RX_DATA_REG (see “Status Receive Data register” on page 451).

Master/slave interrupt codes

Code

Name

Master/slave

Description

0x0

NO_IRQ

N/A

No interrupt active

 

 

 

 

0x1

M_ARBIT_LOST

Master

Arbitration lost; the transfer has to be repeated

 

 

 

 

0x2

M_NO_ACK

Master

No acknowledge by slave

 

 

 

 

0x3

M_TX_DATA

Master

TX data required in register TX_DATA

 

 

 

 

0x4

M_RX_DATA

Master

RX data available in register RX_DATA

 

 

 

 

0x5

M_CMD_ACK

Master

Command acknowledge interrupt

 

 

 

 

0x6

N/A

N/A

Reserved

 

 

 

 

0x7

N/A

N/A

Reserved

 

 

 

 

0x8

S_RX_ABORT

Slave

The transaction is aborted by the master before

 

 

 

the slave performs a NO_ACK.

 

 

 

 

0x9

S_CMD_REQ

Slave

Command request

 

 

 

 

0xAx

S_NO_ACK

Slave

No acknowledge by master (TX_DATA_REG is

 

 

 

reset)

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Image 455
Digi NS9215 manual T e r r u p t codes, Master/slave interrupt codes, Code Name Master/slave Description

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