Disabling the

MMU

WO R K I N G W I T H T H E C P U

TLB structure

Care must be taken if the translated address differs from the untranslated address, because several instructions following the enabling of the MMU might have been prefetched with MMU off (VA=MVA=PA). If this happens, enabling the MMU can be considered as a branch with delayed execution. A similar situation occurs when the MMU is disabled. Consider this code sequence:

MRC p15, 0, R1, c1, C0, 0

; Read control register

ORR R1, #0x1

; Set M bit

MCR p15, 0,R1,C1, C0,0

; Write control register and enable MMU

Fetch Flat

 

Fetch Flat

 

Fetch Translated

 

Note: Because the same register (R1: Control register) controls the enabling of ICache, DCache, and the MMU, all three can be enabled using a single MCR instruction.

Clear bit 0 (the M bit) in the R1: Control register to disable the MMU.

Note: If the MMU is enabled, then disabled, then subsequently re-enabled, the contents of the TLB are preserved. If these are now invalid, the TLB must be invalidated before re-enabling the MMU (see “R8:TLB Operations register” on page 97).

T L B s t r u c t u r e

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The MMU runs a single unified TLB used for both data accesses and instruction fetches. The TLB is divided into two parts:

An eight-entry fully-associative part used exclusively for holding locked down TLB entries.

A set-associative part for all other entries.

Whether an entry is placed in the set-associative part or lockdown part of the TLB depends on the state of the TLB Lockdown register when the entry is written into the TLB (see “R10:TLB Lockdown register” on page 101).

When an entry has been written into the lockdown part of the TLB, it can be removed only by being overwritten explicitly or, when the MVA matches the locked down entry, by an MVA-based TLB invalidate operation.

The structure of the set-associative part of the TLB does not form part of the programmer’s model for the ARM926EJ-S processor. No assumptions must be made

126Hardware Reference NS9215

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Digi NS9215 manual B s t r u c t u r e, Disabling

NS9215 specifications

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