S E R I A L C O N T RO L M O D U L E : U A RT

Interrupt Enable register

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

Enable overflow error

D19

R/W

OFLOW

0

 

 

 

 

Enables interrupt generation if the 4-character FIFO in the

 

 

 

 

UART overflows.

 

 

 

 

Note:

This should not happen in a properly configured

 

 

 

 

 

system.

 

 

 

 

 

D18

R/W

PARITY

0

Enable parity error

 

 

 

 

Enables interrupt generation when a character is received

 

 

 

 

with a parity error.

 

 

 

 

 

D17

R/W

FRAME

0

Enable frame error

 

 

 

 

Enables interrupt generation when a character is received

 

 

 

 

with a framing error.

 

 

 

 

 

D16

R/W

BREAK

0

Enable line break

 

 

 

 

Enables interrupt generation when a line break condition

 

 

 

 

occurs.

 

 

 

 

 

 

D15

R/W

BGAP

0

Enable buffer gap

 

 

 

 

Enables interrupt generation when a buffer gap timeout

 

 

 

 

event occurs.

 

 

 

 

 

D14

R/W

RXCLS

0

Software receive close

 

 

 

 

Enables interrupt generation when software forces a buffer

 

 

 

 

close.

 

 

 

 

 

 

D13

R/W

CGAP

0

Enable character gap

 

 

 

 

Enables interrupt generation when a character gap timeout

 

 

 

 

event occurs.

 

 

 

 

 

D12

R/W

MATCH4

0

Enable character match4

 

 

 

 

Enables interrupt generation when a receive character

 

 

 

 

match occurs against the Receive Match Register 4.

 

 

 

 

 

D11

R/W

MATCH3

0

Enable character match3

 

 

 

 

Enables interrupt generation when a receive character

 

 

 

 

match occurs against the Receive Match Register 3.

 

 

 

 

 

D10

R/W

MATCH2

0

Enable character match2

 

 

 

 

Enables interrupt generation when a receive character

 

 

 

 

match occurs against the Receive Match Register 2.

 

 

 

 

 

D09

R/W

MATCH1

0

Enable character match1

 

 

 

 

Enables interrupt generation when a receive character

 

 

 

 

match occurs against the Receive Match Register 1.

 

 

 

 

 

D08

R/W

MATCH0

0

Enable character match0

 

 

 

 

Enables interrupt generation when a receive character

 

 

 

 

match occurs against the Receive Match Register 0.

 

 

 

 

 

D07

R/W

DSR

0

Enable data set ready

 

 

 

 

Enables interrupt generation whenever a state change

 

 

 

 

occurs on input signal DSR.

394Hardware Reference NS9215

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Digi NS9215 manual Enable overflow error, Enable parity error, Enable frame error, Enable line break, Enable buffer gap

NS9215 specifications

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