Digi NS9215 manual A p t e r 3 W o r k i n g w i t h t h e C P U

GPIO Configuration Register #15	63
GPIO Configuration Register #16	64
GPIO Configuration Register #17	64
GPIO Configuration Register #18	65
GPIO Configuration Register #19	65
GPIO Configuration Register #20	66
GPIO Configuration Register #21	66
GPIO Configuration Register #22	67
GPIO Configuration Register #23	67
GPIO Configuration Register #24	68
GPIO Configuration Register #25	68
GPIO Configuration Register #26	69
GPIO Control registers	70
GPIO Control Register #0	70
GPIO Control Register #1	71
GPIO Control Register #2	72
GPIO Control Register #3	73
GPIO Status registers	74
GPIO Status Register #1	74
GPIO Status Register #2	75
GPIO Status Register #3	76
Memory Bus Configuration register	76
C h a p t e r 3 : W o r k i n g w i t h t h e C P U	81
About the processor	81
Arm926EJ-S process block diagram	82
Instruction sets	82
ARM instruction set	82
Thumb instruction set	82
Java instruction set	83
System control processor (CP15) registers	83
ARM926EJ-S system addresses	83
Address manipulation example	83
Accessing CP15 registers	83
Terms and abbreviations	84
Register summary	85
R0: ID code and cache type status registers	86
R0: ID code	86
R0: Cache type register	86
Cache type register and field description	87
Dsize and Isize fields	87
R1: Control register	88
Control register	89
Bit functionality	89

6Hardware Reference NS9215