Digi NS9215 H e r n e t I n t e r r u p t S t a t u s r e g i s t e r, Address A060 0A10, Rxbufc

E T H E R N E T C O M M U N I C A T I O N M O D U L E

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Ethernet Interrupt Status register. .

E t h e r n e t I n t e r r u p t S t a t u s r e g i s t e r

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Address: A060 0A10

The Ethernet Interrupt Status register contains status bits for all of the Ethernet interrupt sources. Each interrupt status bit is assigned to either the RX or TX Ethernet interrupt; bits D25:16 are assigned to the RX interrupt and D06:00 are assigned to the TX interrupt.

The bits are set to indicate an interrupt condition, and are cleared by writing a 1 to the appropriate bit. All interrupts bits are enabled using the Ethernet Interrupt Enable register (EINTREN). If any enabled bit in the Ethernet Interrupt Status register is set, its associated Ethernet interrupt to the system is set. The interrupt to the system is negated when all active interrupt sources have been cleared. If an interrupt source is active at the same time the interrupt bit is being cleared, the interrupt status bit remains set and the interrupt signal remains set.

Note: For diagnostics, software can cause any of these interrupt status bits to be set by writing a 1 to a bit that is 0.

Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						RX	RX	RX	RX	RX	RX	RX	RXNO	RX
		Reserved				OVFL_	OVFL_		DONE	DONE	DONE	DONE		BU	RXBR
						DATA	STAT	BUFC	A	B	C	D	BUF	FFUL
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									ST	Not	TX	TX	TX	TX	TX
				Reserved								BUF
									OVFL	used	BUFC		DONE	ERR	IDLE
												NR

Register bit

assignment	Bits	Access	Mnemonic	Reset	Description
	D31:26	N/A	Reserved	N/A	N/A
	D25	R/C	RXOVFL_DATA	0	Assigned to RX interrupt.
					RX data FIFO overflowed. For proper operation,
					reset the receive packet processor using the ERX bit
					in the Ethernet General Control Register #1 when an
					overflow condition occurs.
	D24	R/C	RXOVFL_STAT	0	Assigned to RX interrupt.
					RX status FIFO overflowed.
	D23	R/C	RXBUFC	0	Assigned to RX interrupt.
					I bit set in receive Buffer Descriptor and buffer
					closed.
	D22	R/C	RXDONEA	0	Assigned to RX interrupt.
					Complete receive frame stored in pool A of system
					memory.

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