Digi NS9215 manual H e r n e t s l a v e i n t e r f a c e, T e r r u p t s

E T H E R N E T C O M M U N I C A T I O N M O D U L E	. .
Ethernet slave interface..
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– A packet consisting of multiple, linked buffer descriptors does not have the F bit set in any of the non-first buffer descriptors.

When an underrun occurs, it is also possible for the Ethernet transmitter to send out a corrupted packet with a good Ethernet CRC if the MAC is configured to add the CRC to the frame (that is, CRCEN in MAC Configuration Register #2 is set to 1).

E t h e r n e t s l a v e i n t e r f a c e

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The AHB slave interface supports only single 32-bit transfers. The slave interface also supports limiting CSR and RAM accesses to CPU “privileged mode” accesses. Use the internal register access mode bit 0 in the Miscellaneous System Configuration register to set access accordingly (see "Miscellaneous System Configuration and Status register," beginning on page 184).

The slave also generates an AHB ERROR if the address is not aligned on a 32-bit boundary, and the misaligned bus address response mode is set in the Miscellaneous System Configuration register. In addition, accesses to non-existent addresses result in an AHB ERROR response.

I n t e r r u p t s

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Separate RX and TX interrupts are provided back to the system.

Interrupt sources This table shows all interrupt sources and the interrupts to which they are assigned.

Interrupt condition	Description	Interrupt
RX data FIFO overflow	RX data FIFO overflowed.	RX
	For proper operation, reset the receive packet processor using the
	ERX bit in the Ethernet General Control Register #1 when this
	condition occurs.
RX status FIFO overflow	RX status overflowed.	RX
Receive buffer closed	I bit set in receive buffer descriptor and buffer closed.	RX
Receive complete (Pool	Complete receive frame stored in pool A of system memory.	RX
A)
Receive complete (Pool	Complete receive frame stored in pool B of system memory.	RX
B)
Receive complete (Pool	Complete receive frame stored in pool C of system memory.	RX
C)
Receive complete (Pool	Complete receive frame stored in pool D of system memory.	RX
D)

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